Indium Corporation
From One Engineer to Another®

锡膏印刷速度的一个小故事 A Story of Solder Paste Printing Speed

Monday, April 2, 2012 by Anny Zhang [Anny Zhang]

Stencil printing Indium Corporation SMT solder pasteSMT: A Story of Solder Paste Printing Speed

近期我们有一个客户在解决一个和锡膏、芯片、工艺流程等相关的不良率问题。这是一款十分热门的电子消费类产品,在中国的两个主要加工厂量产。

我们公司十分积极帮助客户探讨最优的解决方案,除了及时送样品,我们的技术团队和销售团队还经常拜访客户,提供试样现场技术支持等。但是让我们很吃惊的一点是,客户在做各种试样测试时,锡膏的印刷速度居然是25mm/sec,这是行业里我见过的最低的印刷速度,虽然美国很多中小 加工厂都在用这个速度,因为他们的最终产品是高精尖的军用、航天、医疗器械等,数量不多,而且印刷速度不是瓶颈。

但是在中国或是很多亚洲国家生产的电子消费类产品 (consumer electronics),都是 low mix high volume 的大规模量产,每一条SMT线就像一台印刷钞票的机器,越短的 cycle time, 就能生产处越多的产品,那就更有更高的生产率(high productivity)。印刷速度有时候是瓶颈,所以在亚洲的加工厂,一般印刷速度比较快。

就拿这个客户在中国的两个加工厂来说,印刷速度在 50mm/sec120mm/sec之间。 也就是说在这个印刷速度的条件下(虽然这只是条件之一)出现了问题……不同的印刷速度,很多时候会影响到锡膏的性能,因为印刷速度和压力能够影响到 shear force and shear speed,这些都是下锡量多少的重要决定因素。而下锡量多少,对很多锡膏性能表现的好坏都会起到决定性的作用,特别是客户现在在研究的不良率。

锡膏和底部填充剂的兼容性 (Solder Paste Compatiblity with Underfill in SMT)

Thursday, January 19, 2012 by Anny Zhang [Anny Zhang]
SIR Testing SMT中,底部填充剂(underfill) 常常被用在BGA/QPN 的组装中,这样可以更好的保护BGA/QFN 下面“脆弱”的焊接点。 因为现在很多消费电子产品都是使用免洗锡膏 (No-Clean Solder Paste),锡膏的残留物会留在板子上,不需要被清洗;所以当OEM 厂商在设计使用underfill时,都会考虑到锡膏残留物和underfill的兼容性(compatibility)。有些厂商会问供应商们拿数据;更多的是自己直接做可靠性试验(reliability tests SIR表面绝缘测试(surface insulation resistance) 是常用的一个测试。因为underfill 基本上填充了除了焊点和残留物的其他空间,所以在填充后,要证明焊点之间是绝缘的就很重要,不然会造成短路。 有时候用了underfillSIR测试没有通过,OEM 厂商们立刻会追问是不是锡膏残留物不兼容。其实不尽然也。Indium 公司的许多常用的焊锡膏都和很多常用的underfill 材料做过兼容测试,很多通过了SIR测试,我们也有保留相关的数据。有时候发现不兼容(没有通过SIR 测试),我们有请第三方 公司来帮忙分别做残留物和 underfillSIR测试,结果都是因为underfill自己本来就没有通过SIR ,所以使用在元器件下面也自然会没有通过。 让我们用数据来 说话 (it’s always data driven!!) 龙年快到了,祝各位龙的子孙新春快乐,龙腾虎跃,龙马精神,龙年大吉!! The Year of Dragon Cheers!



Pic: Google Images

Military/Aerospace Lead-Free Solder Reliability Still Unproven

Monday, December 12, 2011 by Dr. Ron Lasky [Dr. Ron Lasky]
Manhatan Chart

Folks,

I’m taking a few moments from Wassail Weekend , held annually in my village, Woodstock VT, “The prettiest small town in America”, to write a post about last week’s workshops at ACI.

Indium colleague Ed Briggs and I gave a 3 hour presentation on “Lead-Free Assembly for High Yields and Reliability.” I think Ed’s analysis of “graping” and the “head-in-pillow” defect is the best around. 

There was quite a bit of discussion on the challenges faced by solder paste flux in the new world of lead-free solder paste and miniaturized components (i.e. very small solder paste deposits.) One of the hottest topics was nitrogen and lead-free SMT assembly. There seemed to be uniform agreement that solder paste users should be able to demand that their lead-free solder paste perform well with any PWB pad finish (e.g. OSP Immersion silver, electroless nickel gold, etc.) without the use of nitrogen. Not only does using nitrogen cost money, but it will usually make tombstoning worse. However, in the opinion of most people, nitrogen is a must for wave soldering and, since it minimizes dross development, it likely pays for itself.

After Ed and I finished, Fred Dimock, of BTU, gave one of the best talks I have ever experienced on reflow soldering. He discussed thermal profiling in detail, including the importance of assuring that thermocouples are not oxidized (when oxidized they lose accuracy). He also discussed a reflow oven design that minimizes temperature overshoot during heating, and undershoot when the heater is off. Understanding these topics is critical with the tight temperature control that many lead-free assemblers face.

Fred Verdi of ACI finished the meeting with an excellent presentation on “Pb-free Electronics for Aerospace and Defense.” Fred’s talk discussed the work that went into the “Manhattan Project.” A free download of the entire project report is available.

There appears to be agreement that acceptable lead-free reliability has been established for consumer products with lifetimes of 5 years or so, but not for military/aerospace electronics where lifetimes can be up to 40 years in harsh service conditions. These vast product lifetime and consequences of failure differences are depicted in the Fred's chart (above). Commercial products are in quadrant A and military/aerospace products in quadrant D.

One of the greatest risks faced by quadrant D products is tin whiskers. Fred spent quite a bit of time discussing this interesting phenomenon. One of the challenges of this risk is that there is no way to accelerate it, so you can’t do an equivalent test to accelerated thermal cycling or drop shock. Fred mentioned that there have now been verified tin whisker fails, the Toyota accelerator mechanism being a confirmed one.

In addition to tin whiskers, lead-free reliability for quadrant D products (with a service life of up to 40 years) in thermal cycle and other areas remains a concern.  I mention that tin pest was not on the list of issues for this quadrant.

Fred and the Manhattan Project Team have identified many "gaps" that need to be addressed to determine and mitigate the risk of lead-free assembly for quadrant D products.  They plan to start this approximately $100M program in 2013.

For those that missed this free workshop, ACI host Mike Prestoy is planning another one in 6 months.

Cheers,

Dr. Ron


Tombstoning: The Death of a PCBA

Wednesday, November 30, 2011 by Eric Bastow [Eric Bastow]
Tombstoning DiodeTombstoning (also known as the Manhattan effect, drawbridge effect, or Stonehenge effect) is described (in the simplest, and most common, sense) as occurring when one end of a passive device, such as a resistor or capacitor, rises up out of the solder and breaks contact with the circuit. But it is not limited to passive devices. Other surface mount devices can tombstone as well (see the tombstoning diode image - top). Tombstoning is a "fatal" defect because it produces an open circuit.

Tombstoning has, once again, become a central issue - primarily due to two main issues:
  • Tombstoningthe transition to Pb-Free (higher reflow temperatures, and related flux issues)
  • miniaturization (0201s and 01005s)
Tombstoning is almost always the result of uneven wetting forces on the terminations of the component. When one end "wets" before the other, the (now unbalanced) wetting force of the solder "pulls" the component, rotating it, causing it to stand on end.

Various factors contribute to tombstoning. The one that we (as a solder paste supplier) typically encounter  is uneven heating of the PCB assembly - which causes one paste deposit to melt and wet before the other - per component (as described above). Trying to achieve a higher reflow temperature, as required with the new mainstream Pb-Free alloys, can exacerbate the greater thermal gradient across the PCB (and from one end of a component to the other).

Reflow ProfileThermal gradients are usually easily remedied with minor adjustments to the reflow profile:
  • The reflow oven operator can slow down the ramp rate. A slower ramp rate allows for more uniform warming of the PCBA.
  • Another technique is to employ a "soak" just below the melting temperature (solidus) of the alloy. For example, for a SAC305 profile (217°C solidus), one may implement a "soak" at 205 to 210°C for 30 to 120 seconds. This allows for the cooler parts of the PCBA to "catch up" to the warmer parts. After thermal equilibrium has been achieved, one can spike the temperature up to the appropriate peak temperature (i.e. 245°C). This technique (depicted in the reflow profile shown at the right) allows for all of the solder paste deposits to melt and wet the component terminations at roughly the same time; thereby, mitigating tombstoning.



Different flux chemistries, and types, can also impact tombstoning. It is often desirable to have a solder paste that wets well, even to old, oxidized components. One possible negative side effect of an excellent wetting solder paste is tombstoning. When the paste wets "aggressively" to the component terminations, causing a strong wetting force, even the slightest disparity (temperature, cleanliness, flux area, etc.) from one termination or pad to the other can cause the component to tombstone.

The wetting speed and force is also directly related to the rate at which the solder melts. It should be obvious that wetting only occurs when the solder is in a liquid state, not while solid. For this reason, solder alloys that are not eutectic (alloys that start to melt at one temperature but are not fully liquid until some higher temperature) can produce less tombstoning than a eutectic (clearly defined melting point) alloy, all other things being equal. Sn63 (63Sn 37Pb) is a eutectic alloy and makes a clean transition from a solid to a liquid at 183°C. Sn60 (60Sn 40Pb) is not eutectic and starts to melt at 183°C but is not fully liquid until 191°C. In the case of "non-eutectic" alloy like Sn60, between 183°C and 191°C, solid and liquid are coexisting. To this end, some solder paste manufacturers have developed alloys that melt gradually (are purposely not eutectic) to combat tombstoning.  

Wetted Passive ComponentThe pad design and lay-out can also affect tombstoning. Usually pads that are located mostly beyond the terminations or have large pad areas beyond the terminations can contribute to tombstoning. To the left is an image of a cross section of a soldered passive component. Notice how the solder fillet reaches to the top of the termination. Solder paste deposits that extend well beyond the component cause a lot of wetting force and leverage to be applied to the extreme ends and tops of the component. This wetting force, if not evenly applied to both terminations, can cause the component to tombstone.









Reduced Solder VolumeSimilar to the placement of the solder paste deposit (pad design), solder volume can also impact tombstoning. It is very simple. More solder equates to more wetting force and vice versa. To the right is an image that has an extremely reduced amount of paste volume (not recommended to this degree). If one could imagine that this component had indeed properly soldered to the pads, one could see how it would be nearly impossible for the component to tombstone. There is simply not enough solder to wet the entire end of the termination. Solder deposit volumes that restrict the solder from being able to wet up to the top of the component greatly reduce the wetting force and leverage that the solder can apply to the component. Depending on the class of workmanship that one is building to, it may not be practical to reduce the solder volume. The product class may require fully wetted terminations.



It is also critical that the solder paste deposit and component sit squarely on the pads. Any offset can affect the way the solder wets the terminations and can cause tombstoning.

Offset Solder Paste Deposit


Miniaturization, as characterized by smaller, lighter passive components, such as 0201s and 01005s, creates a struggle where tombstoning is concerned. Issues of solder paste deposit location (see image to the right), component placement, and solder paste volume are difficult to control given the overall minuscule scale of the scenario. Also, smaller components are inherently lighter and, therefore, easier to pull up on end.

Controlling tombstoning is a critical issue in SMT assembly. But, with understanding what causes tombstoning, one can control it.

CONTACT ME to discuss tombstoning:

Eric Bastow: Senior Technical Support Engineer

Phone: +1.315.853.4900
E-mail: ebastow@indium.com

Solder Paste and Flux Dip Depth: II

Tuesday, November 15, 2011 by Dr. Andy Mackie [Dr. Andy Mackie]

Following on from our discussions of last time...

As you will recall from the previous post on this topic, My friend and colleague Chris Nash and I were discussing some puzzling results for low dip height found during testing of package-on-package (PoP) materials. The findings will be of interest to everyone who uses a dipping process in both SMT and flip-chip assembly.

Post II:
For greater solder paste and flux dipping heights it appears as though a linear doctor blade (back and forth) used in a dipping process running at high speed will allow dip heights close to those expected from the theoretical engineered limit, for 50 microns and greater dip height. The high speed shear-thins the flux, which has the effect of both reducing the thickness of the boundary layer, and also has the benefit of reducing the extensional (tack) viscosity, so components can be more easily released from the dip tray.

What if you want to go to lower dip depths?

As we move into the area of copper pillar flip-chip dipping, and even (we hear) some Japanese customers doing package-on-package assembly, the dip height (dip depth) can go down to as low as 10-20microns, and this where we are hearing that rotary dip trays are coming into their own. The diagram below shows a simplified version of a flux and solder paste dipping tray.
Rotary dipping tray

Rotary dip trays seem to have the following advantages:

- Height Setting: The dip height/depth is set using two micrometers, so is infinitely adjustable to a precise setting, although the dip height does have to be measured.

- Low Cost: They also add zero capital cost for a new dip depth setting, compared to specially-engineered dipping trays, which can be upwards of $2,000 each.

- Accuracy and Precision of Depth: From a more pragmatic viewpoint, however, the real reason for rotary trays being used with ultra-low dip heights is that the flux depth is actually measured: there is no tacit assumption of a given dip depth being correct and constant, based on the engineering of the dipping tray. As we saw last time, an error of 20 microns is possible, and with a dip height of 50 microns or less, this is a huge problem if you are using a 50 micron dip tray and assuming that you are getting exactly that dip depth.

However, rotary dip trays also have their share of potential problems compared to linear dipping systems: 

 - Larger Surface Area: Flux and solder paste may dry out faster, and a water soluble material will be more vulnerable to the humidity content of the air. It is also more wasteful of flux, since a larger surface area of flux is exposed than will ever be used, although this may also be true of some of the linear tray designs.
 
- Circular Tray: Materials will experience a higher shear rate at the outer edge than in the middle. If spun too fast, dipping materials may accumulate at the edges, thrown outwards by centripetal force.

- Lower Shear Rate: For the same flux or solder paste dip depth, the velocity of the doctor blade will be much lower with a rotary than a linear system. However, as you can see from the illustration below, for a doctor blade moving at 1/4 the speed and 1/4 the dip height, the shear rate is the same.
Shear rate and depth and velocity

As always, please contact me if you need to learn any more.

Cheers!  Andy


Solder Paste and Flux Dip Depth: I

Wednesday, November 9, 2011 by Dr. Andy Mackie [Dr. Andy Mackie]
My friend and colleague Chris Nash and I were recently discussing some puzzling results for low dip height found during testing of package-on-package (PoP) materials. The findings will be of interest to everyone who uses a dipping process in both SMT and flip-chip assembly. Firstly, a little background. Many of you will be familiar with the two types of dipping tray used in both PoP and flip-chip assembly:

Rotary Type - This has a doctor blade that is fixed in place, but adjustable in height, attached to a rotating dip tray of flux or solder paste that spins under the blade, providing a level surface and a known thickness of material into which the component is dipped.

Linear Type - Although the doctor blade in a system of this type is usually the moving component, there are some tools where the dip tray itself moves from side to side under a fixed "blade" or reservoir. EB Datacon flip-chip dipping equipment, for example, may be of either type.

Advantages have been claimed for both types of system, but the rotary type seems to be winning out over the linear type for very precise dip depth control. That said, linear seems to be much more common. Why should this be?

One clue that we recently discovered is that the dip depth for a linear system is always less than the designed depth: whether the fluid in it be a flux or a dipping solder paste. The assumption is that the depth of flux in the linear dip tray is exactly the same as the design height (below).
Ideal dipping

However, as evidenced by both visual inspection of the solder ball / flip-chip bump dip height, and also by direct measurement of the fluid in the dip tray, the actual flux or paste dip height is always less than the design height (below). Why should this be?
Dip Depth 2 - actula situation
The answer can probably be found in reference to the concept of a boundary layer (red circle above): a layer of material immediately adjacent to a surface that is either completely immobile (static boundary layer) or moving at a velocity less than in the bulk of the moving fluid. With no boundary layer, there would be no drag (fluid frictional forces) and of, course, that is why golf balls have dimples: so that the boundary layer is kept mostly beneath the outer surface of the ball, to reduce drag. This principle has also been adopted for some squeegee blades.

The reduction in height is of the order of 10-20microns, as closely as we can tell with the measurement systems available. So, for a 200micron dip depth, this will only lead to an error of -5 or -10% in the actual dip height.

Since most dipping materials are thixotropic, there is the added complication of time dependence of the material's rheology. The fastest way to reach the equilibrium dip depth is to use a very fast movement of the doctor blade system relative to the dipping tray, although this will almost inevitably increase the prevalence of bubbles.

Again, the linear system is most commonly seen for most PoP and flip-chip dipping applications, but it clearly has its limitations, as we will discuss in part II.

I welcome your comments.
Cheers!  Andy

QFN Reliability in SMT Electronics Assembly

Monday, October 24, 2011 by Dr. Ron Lasky [Dr. Ron Lasky]

Folks,

Let's look in on Rob:

Rob looked at the new photo of Patty and their twin sons Peter and Michael. What a handful those two 18 month-olds were. Just like their mother! Rob was still pinching himself that he was lucky enough to have Patty as his wife. Rumors were that she would make VP soon, and a few of his buddies asked him if her success bothered him. 

He would always respond, “Let’s see: beautiful, successful, athletic, fun to be with, great mother, and most of all she loves me. What’s not to like?”

Rob really meant it. He felt Patty deserved her success. One of her great assets was her high energy level. She went to bed at 11:30PM and was up at 5AM to run two miles, lift weights, shower, and then take care of the kids. Rob just couldn’t keep up on less than seven and a half hours of sleep. So he got up at 7AM. Rob had to insist that they have some quiet time each night after the boys were in bed, to talk and maybe even watch some mindless TV. But Patty would often sneak her laptop out to work while NCIS was on. Patty, the workaholic!

Rob and Patty spoke Mandarin at home one day each week and Spanish another night. The boys were picking up all three languages. It was amazing to both Patty and Rob as they watched this miracle.

Well anyway, Rob did have one thing up on Patty: math. Rob was close to a math genius and also good at writing software. He was the “go to” guy for math modeling and writing software for the math models. He even helped the Professor improve ProfitPro. Rob also wrote a program that could be used to design an SMT line for maximum throughput. The software could do what Arena did in hours of simulation, in seconds.

Rob was startled from his daydreaming by the phone ringing. It was Sam the site GM.

“Hey Rob, we need your help in our plant in Guadalajara. Can you come right down to discuss it?” Sam asked.

“I’ll be right there,” Rob replied.

Rob walked to Sam’s office with a feeling of exhilaration. It was always fun and exciting to be sent on a trouble shooting mission.

QFN“Rob, thanks for coming right down. This issue is QFN reliability. About 5% of the Druid mobiles phones in our Guadalajara plant are coming back with some of the QFNs burned out,” Sam began.

“Sounds like a voiding issue under the QFN thermal pad,” Rob interrupted.

“Wow, you seem to know quite a bit about this type of problem,” Sam remarked.

“Remember how I pleaded with you to go to SMTAI,” Rob teased.

“Yep,” Sam replied.

Seth Homer gave a talk on this issue at the show last week. It was a terrific overview of the problem. From what you described the connection may need more solder. We may have to use solder fortification preforms to solve this. Optimizing the solder paste printing process may not be enough,” Rob summarized.

“Well, go there and solve the problem. The warranty issues are costing us a fortune,” Sam commanded.

After a moment of contemplative silence, Sam asked, “Do you need anything?”

“It would be nice to have Pete come. He knows the people there and is well connected. His Spanish is also terrific,” Rob said.

“OK, no problem. Since you sleep with Pete’s boss, you can work out the details with her. I need you to go this week,” Sam said.

“No problem,” Rob said.

As Rob left the office, he was elated with his new assignment. He had to admit though, he thought it was unprofessional and a little annoying of Sam to say, “since you sleep with Pete’s boss, you can work out the details with her,” but it wasn’t the first time someone said this. Truth be told, Patty might be a little annoyed. She really depended on Pete.

Will Patty be angry at Rob for taking Pete to Guadalajara? 
Will Rob solve the QFN problem?
How does Patty get by on only 5.5 hrs of sleep each night?
Stay tuned for the exciting conclusion.

Cheers,

Dr. Ron

Soldering: an Indian Engineer's Perspective!

Monday, October 24, 2011 by Liyakathali Koorithodi [Liyakathali Koorithodi]

Hi there!

I am excited, this is my first blog post -ever. I am excited that it is a technical blog of Indium Corporation.

Solder Wire SpoolMy story is very interesting; a common village boy has grown to become part of a BIG corporation in which everyone is obsessed with soldering! It was my passion to learn electronics assembly techniques 10 years ago. I strived and spent many sleepless nights on this – I would say on SMT.  When our Marcom Superstar Anita told me about the blogging opportunity I was really excited… how would I…? Anyway I am here!

So … soldering and solder paste is my passion. I have published two technical papers on solder paste and reflow. And you will see more thru this blog.

My two cents on soldering… although soldering process looks simple and any one can define with a single sentence; it is not a simple process. It is comprised of chemical, physical, and metallurgical process and deals with fluxing, melting of alloy, wetting, spreading, surface tension, coalescence, wicking, intermetallic growth/bonding, time above liquidus (TAL), cooling down for smooth grain structure etc.

We will have more discussions in upcoming post; stay hungry, stay foolish!

Best Regards
Liyakathali.K (Liya)
Sr.Technical Support Engineer - India
Based in Chennai, Tamil Nadu

Tin and Silver Use in Electronics after RoHS

Thursday, September 22, 2011 by Dr. Ron Lasky [Dr. Ron Lasky]

Folks,

In a recent posting we discussed that the higher melting temperatures of lead-free solder require reflow soldering temperatures to be higher, thus more electricity is used in lead-free assembly. However, as we calculated, this increased use of electricity is very small compared to all electricity used in the world.

An additional concern that some have voiced is the claim that RoHS, with its lead-free requirement, actually makes the environment worse because more tin and silver is used in lead-free solders.   They argue that the increased use of these metals, creates mining pollution and has driven the price of these metals sky high. Let’s examine these claims.

Figure 1 Tin UsePrismark has estimated that approximately 90,000 tons of solder are used in electronics, with about 80,000 used in wave soldering and 10,000 tons for SMT soldering. It is important to remember that electronics solder is a subset of all solder. All solder (alloys for brazing pipes etc) uses about 190,000 tons of tin. Solder is the single largest user of tin. See Figure 1. 

Figure 1. Solder is the largest end use of tin. Tin is the base material for almost all solders. 

If tin-lead solder were still used predominantly, approximately 57,000 tons of tin (90,000 x 63% tin) would be used annually. With lead-free solder, about 88,000 tons (90,000 x 98% tin) of tin are used per year. This is an apparent increase of about 30,000 MT of tin used each year. However, an interesting thing to consider is that lead-free solder is about 14% lighter than tin-lead solder. Knowing that, and knowing that solder used in wave soldering (remember wave soldering accounts for almost 90% of all solder used in electronics assembly) is consumed by volume not weight (i.e. assuming approximately the same fillet size), about half of this increase is canceled out. 


This is all a bit confusing however, so it may be best to just to look at tin use. According to the United States Geological Survey (USGS), about 300,000 tons of tin are mined each year. Figure 2 is a graph of world tin production at mines per year (this graph does not show recycled tin.)  The amount of refined tin used each year in the US is depicted in Figure 3. Figure 3 includes about 15,000 tons a year of recycled tin. Recycling solder is very cost effective. Scott Mazur just pointed out (Printed Circuit Design and Fab and Circuits Assembly, p 36, August 2011), that recycling solder dross is 10 times as cost effective as recycling aluminum cans.

Looking at these graphs, it is hard to say that the amount of tin used has gone up since RoHS. It would appear that tin use is likely more affected by the economy and that it is really difficult to see an effect from RoHS’s July 2006 enactment.


Figure 2. World Tin Production at Mines. 

Figure 2 Tin Mine ProductionMost wave soldering solders have low or no silver. So, about 3% of the 10,000 tons of SMT solder, or 300 MTs of silver, are used in electronics. This is about 1.5% of the 22,000 MTs of silver produced each year. Silver use in electronics does not make anyone’s list of top silver usage.















Figure 3. US consumption of tin has decreased since RoHS was enacted.

Figure 3 US Tin UseSo electronics solder use since RoHS has not caused tin use to increase, nor is it a significant factor in silver use. Therefore it is highly unlikely that electronics' use of tin or silver has been a prime driver in their stunning price increases in 2011.

Cheers,

Dr. Ron

Type 8 Solder Paste 8号粉焊锡膏

Tuesday, September 13, 2011 by Anny Zhang [Anny Zhang]

Solder Powder最近已近有两个客户在询问Indium公司有没有Type 8 Solder Paste 8号粉焊锡膏,分别用在医疗器械上和wafer level方面。

SMT中,我们通常使用的都是3号粉和4号粉。在IPC的规格中, 3号粉的规定是球半径在25-45micron之间;4号粉的规定是球半径在20-38micron之间。其实这中间也有很大一部分重合。 一般来说,随着锡粉球半径越小,相同重量锡粉中球的表面积就会越大,在焊接过程中锡球就越容易被氧化,那么对锡膏助焊剂(solder paste flux)的要求就越高,不然很容易出现solder balling/graping等现象。

IPC中是没有对7号粉或是8号粉的锡球定义,但是随着微型化,客户们确实是有这方面的需求了。

Cheers!

Pic: Indium Corporation

Increased Use of Electricity for Lead-Free Soldering Assembly & High-Melt Lead-Free Solders

Wednesday, August 10, 2011 by Dr. Ron Lasky [Dr. Ron Lasky]

Folks,

An obvious disadvantage of lead-free electronics soldering assembly is that the oven must be hotter and therefore will use more electricity (versus 63Sn37Pb soldering). But is the extra amount of electricity significant? Bill O’’Leary claims that a typical SMT oven uses $7K of electricity a year at $0.072/Kilowatt hour (Kwh) or about 100,000 Kwh. That number strikes me as about right, as a household uses about 5-20,000 Kwh per year.

In the late 1990s there were 35,000 SMT lines in the world, at a 3% growth rate that would be about 50,000 lines now. So worldwide SMT reflow oven use would be about 5E9 KWhr (50,000 ovens x 100,000 Kwh/per year) world wide.  

With most heat loss be due to convection, the increase in energy use will be approximately proportional to the difference between the oven temperature and the room temperature (25C). An oven processing tin-lead solder would run at about 210C versus lead-free’s 250C. So the added energy for a lead-free oven would be about (250-25)/(210-25) or about 22% more. So if all assembly lines in the world are SMT the added energy use would be about 0.22x 5E9 Kwh Dr. Ning-Cheng Lee: INDIUM CORPORATION= 1E9 Kwh. The cost of this extra electricity would be about $100 million (US) at $0.10/ Kwh. The electronics industry generates about $1.5 trillion in sales. So this added cost would be about 0.0067% of sales. Since world electrical use is about 150,000 E9 Kwhr per year, this increase is about 1/150,000 of all of the electrical use or 0.00067%.

So although more electricity is used, the increase is not significant to the value of the electronics sold or the total world use of electricity.

Thinking about higher temperatures reminds me that my Indium Corporation colleague Dr. Ning-Cheng Lee is presenting a paper this week on a high melting temperature lead-free solder based on a BiAgX alloy system. Higher melting temperature solders are often needed in what is referred to as a solder hierarchy. Solder hierarchies have solders that melt at decreasing temperatures in multiple soldering steps, starting with the highest melting solder.

Cheers,

Dr. Ron

A New Low-Temperature Metallization Paste For Interconnecting Thin-Film Solar Cells

Monday, August 1, 2011 by Jim Hisert [Jim Hisert]

Last week I spent some time in the simulation lab with Eric Bastow, verifying the printing characteristics of our newest low temp metallization paste LT-918. Due to its current success with a variety of customers, we needed to take production capacity to the next level. New equipment was purchased to keep up with the demand, but there is always the chance that material may not perform the same when it is made in substantially larger batches. Our testing confirmed the printing characteristics of the material made on the new equipment surpassed that of previous batches. That’s good news for everybody.

LT-918 Low Temp Metallization PasteAs you can see from the picture, we used a standard printer designed for stencil printing solder paste onto electronic circuit boards. The printer was not the only similarity to solder paste printing though. An interesting characteristic of LT-918 is that it has a higher viscosity than most metallization pastes, which helps with print definition. The high viscosity of LT-918 helps it print like a solder paste, this is great for solder paste printers (like Eric and I, and many of you for that matter) from the SMT and semiconductor assembly industries.

In my opinion, LT-918 is the best metallization paste currently available for interconnecting thin-film cells. It has not only excelled in printing, it also has industry-leading resistivity scores, and has passed customer reliability testing including thermal cycling, damp heat stability, and accelerated UV tests. Much of the data that we can share will be available soon as a product brochure that we hope to have ready for you at EU-PVSEC in September.

Thermocompression Bonding for Microbump Flip-Chip Soldering

Sunday, June 26, 2011 by Dr. Andy Mackie [Dr. Andy Mackie]

For reasons that I will discuss in a post later this year, a common factor that is emerging in the area of copper-pillar microbump 2.5D and 3D joining, is the adoption of thermocompression (TC) bonding for flip-chip flux/microbump soldering. TC bonding is now being predominantly adopted instead of reflow. Some of you may have the same response as I got at iMAPS 2011 from one well-known expert in packaging technology. He looked askance at me when I mentioned TC bonding for flip-chip and retorted: “That’s for bonding wafers, not soldering flip-chips!”. Even good old Wikipedia (at time of writing) seems to have the same problem – basically that the industry usage of the term has moved into the packaging arena.

I spent a little time talking to people in the industry, and on Google, putting together a buyer’s guide for those of you looking at who-is-doing-what in TC bonding. This is just a prototype guide and necessarily incomplete – if I have missed your company out then I apologize, and will add it in: just give me all the details!

Equipment Type Company Name URL Bonding tools What else they make
Die-bonders ASM (PT) http://www.asmpacific.com/asmpt
/index.htm
Die bonders, flip-chip bonders Various others
Die-bonders BESi http://besi.com/  Die and flip-chip bonders (Datacon) Meco (plating systems), Fico (molding / trimming), ESEC
Die-bonders FineTech http://www.finetech.de/  Die bonders, flip-chip bonders (offline) SMT/BGA rework, Laser bar-bonder, VCSEL, Photodiodes, Chip-on-glass, RFID
Die-bonders Hybond http://www.hybond.com/  Eutectic die bonders (offline/manual) Wirebonders / Peg and bar lead diode bonders
Die-bonders Newport http://www.newport.com/ Die bonders Optical and alignment instrumentation, spectrometers
Die-bonders Palomar http://palomartechnologies.com/  Die bonders Ballbonders, stud bumpers, manual die bonders
Die-bonders Panasonic http://www.panasonicfa.com/?id=MD-P200  Die bonders Wirebonders etc etc
Die-bonders SET http://www.set-sas.fr/en/  Die bonders, flip-chip bonders Large device bonders and nano-imprint
Die-bonders Shibaura http://www.shibaura.co.jp/e/products/  Die bonders, flip-chip bonders FEOL products (etching, stripping, coating, jetting) and BEOL
Die-bonders Toray http://www.toray-eng.com/sitemap/index.html#semicon  Die bonders, flip-chip bonders [Semi]Inspection, exposure, encapsulation. COG / COF / FOG bonders
Die-bonders Westbond http://westbond.com/machines.htm  Die bonders (offline/manual) Wirebonders
         
Wafer bonders EV Group http://www.evgroup.com/en  Wafer bonders Lithography tools
Wafer bonders Suss Microtech http://www.suss.com/  Wafer bonders Mask aligners, nanoimprinters, photomasks, lithography tools

Thanks to Brian Schmaltz of Namics kk for one extra addition to the list. 

Cheers! Andy


SMT Reflow Process Window: Solder Paste Maximum Slope vs. Ramp (or Average) Rate

Monday, June 6, 2011 by Ed Briggs [Ed Briggs]
Included in a solder paste's Product Data Sheet, among other things, are general guidelines which aid the customer in designing an SMT reflow profile. The data sheet gives general recommendations, for time above liquidus, peak temperature, and ramp rate.


Example:

Indium8.9 Profile Recommendations








 



Figure 1: Example shown Indium8.9 flux with SAC lead-free alloy


The reason for approaching this subject is that often there has been some confusion in regards to the difference between max slope (a category reported on most profiling software) and the ramp rate listed on a data sheet.

Max Slope






















Figure 2: Max Slope

The max slope is very often attained in the first zone as the PCB moves from ambient temperature into the oven. In most cases the oven zone setting for the first zone is 100°C or better. The change in temperature between ambient and the first zone then is a minimum of 75°C (assuming 25°C as ambient) and so it’s easy to see that the greatest change in temperature (max slope) in most cases is typically found in the first zone

The focus of max slope is more from a component view point, to avoid thermal shock, usually 3°C/s is recommended as the upper limit

Ramp or Average Rate
























Figure 3: Ramp or Average Rate


The ramp rate may be better described as the rate (change in temperature over time) from ambient (room temperature) to peak. And is more practically used in a ramp to spike type profile

From the view point of the solder paste, the lower the ramp rate the better, usually 1-2°C/s. This is to drive off volatiles and help minimize solder defects such as solder balling, solder beading, and tombstoning. This rate becomes even more important as the solder paste deposit continually decreases in size, as we move to 0201’s and smaller discrete components and from 0.5mm pitch area array packages to 0.4mm and smaller. Due to this miniaturization, the observance of graping and head-in-pillow have become more common. The reflow process window is becoming very narrow and this attribute (ramp rate) has become as important as time above liquidus and peak temperature.

I'd love to discuss this with you, if this topic is affecting your SMT process. If you'd like, feel free to contact me.

 

 

Solving Solder Starvation in SMT Electronics Assembly

Wednesday, June 1, 2011 by Carol Gowans [Carol Gowans]
Solder Paste StencilSolder starvation is a serious electronics assembly issue - with a very simple solution.

Solder starvation occurs when adequate volumes of solder are not available to effect a perfectly-shaped solder joint. The consequences include:
  • weak solder joint strength
  • open solder joints
  • intermittent short circuits
  • reduced first-pass yields
  • increased inspection
  • increased rework
  • field failures
  • damage to your company's brand & image
  • reduced sales and profits

Frequently, solder starvation occurs in Surface Mount Technology (SMT) when solder paste deposits are inadequate.  This happens because: 
  • Solder Fortification™ preforms packed in tape & reel packaging, for use in existing SMT production lines.The single-thickness stencil is designed for the majority of smaller components, starving the few larger components of solder volume.
  • High-use interfaces, such as connectors and USB ports, require extra solder - to assure their solder joints survive the constant use in the field.
  • Smaller, more tightly compacted circuit boards don't allow for deposition of enough solder paste.
So, how do you solve this increasingly common problem without impacting your process or your cost? 

Solder Fortification™ preforms are the simple answer:
  • You can add solder just where you need it without overprinting solder paste or working with step stencils.
  • Preforms deliver precise, repeatable volumes of solder.
  • Preforms can be added during your existing SMT process with existing pick & place equipment.
  • Preforms eliminate the need for rework or hand soldering at the end of the process.

For more information, contact me at solderfortification@indium.com or visit our web site at www.indium.com/solderfortification.

Carol Gowans
Market Manager

Silver-free and Low-Silver Solder Alloys for SMT Discussion, Part 1: Reliability

Thursday, May 19, 2011 by Mario Scalzo [Mario Scalzo]

There seems to be a growing trend to use a low-Ag or Ag-free solder alloy for Surface Mount Technology (SMT) electronics assembly, similar to what is commonly offered for bar solder, used in wave and selective soldering.

For through-hole performance, the strength and stability come from the entire barrel of solder, whereas it is usually the foot and heel fillets that give SMT solder joints their strength.

Printed Solder Paste.Lets talk about the other issue with using a eutectic solder alloy in SMT: tombstoning.  One of the benefits of using the SAC (tin-silver-copper) alloy for SMT and solder paste, is that it has a built-in plastic range, similar to that of Sn62 (62Sn 36Pb 2Ag).  It is this plastic range that prevents tombstoning, and takes into account the inconsistent heating of the solder across the part (which is the sole cause of tombstoning).  Switching to a eutectic alloy eliminates the plastic range and opens the door for tombstoning.

Any powder manufacturing issues, such as the inconsistent distribution of dopants throughout the alloy and powder matrix, takes a back seat to the surface mount reliability concerns. 

There are other alternatives, such as SAC0307 (99Sn 0.3Ag 0.7Cu)… But, with the price of Ag finally coming down, and a long history of SAC usage, we don’t think it’s going to be a major player.

Next time, we'll talk about the manufacturing and costs associated with low-Ag and Ag-free alloys. 

I hope this helps. Contact me with any questions.

Indium公司在 Nepcon上海将举行SAC105+Mn记者招待会

Wednesday, May 11, 2011 by Anny Zhang [Anny Zhang]

下周在上海将会有SMT行业中一年一度的大盛事,Nepcon上海展会。 

Indium 公司将在5月12号周四上午11点,在展位2E06举行一个关于SAC105+Mn的记者招待会。

Indium公司几年前就研发了关于SAC105+Mn的合金,并申请了专利。这里有相关的文章“Achieving High Reliability Low Cost Lead-Free SAC Solder Joints Via MN or CE Doping
”与您分享,由Indium公司的Dr.Weiping Liu 和 Dr.Ning-Cheng Lee李宁成博士等共同著作。  

这些年来随着金属成本的上升,中国市场对低银的可靠性高的焊接材料的需求,Indium公司也对SAC105+Mn的焊锡膏等焊接材料做了一系列的研究。实验数据表明,用SAC105+Mn合金做出来
的焊锡膏,跌落测试(drop test)比SAC305好很多,热循环测试(thermal test)与SAC305媲美。目前已经有相当一部分中国客户在使用这款焊锡膏了,工厂的产率与原来用SAC305时的相差无几。
更多的信息,我们将于您在记者招待会上分享。热切期待届时与您相见。

Cheers!

SAC105 + Mn paste
problem-solved_Great performance in drop test

Pic: Indium Corporation

PS;我以前在博客中也与大家分享过几篇关于SAC105+Mn的小文,请看这里1,2。谢谢您持续的关注!今年宝宝快出生了,不能与您在Nepcon上海中相聚,盼来年再见!

选择性焊接 Selective Soldering

Wednesday, March 30, 2011 by Anny Zhang [Anny Zhang]

最近越来越多的客户提到了选择性焊接Selective Soldering我之前对此了解比较少,所以特意问了同事们学习了一下,发现选择性焊接有以下几点:

---和波峰焊焊接(wave soldering)比较相似,通常在SMT贴片回流后。

---和波峰焊焊接的不同点在于,selective soldering不需要整个板子都经过solder wave; 而是有一个固定的nozzle,对需要焊接的那一小部分进行”wave” soldering

---选择性焊接(Selective soldering)是整个板子不用经过第二次温度剧增(thermal excursion),不单单保护了板子 (reduce CTE mismatch),而且保护了已经焊接在板子上的对温度变化敏感的原件。

---选择性焊接(Selective soldering) 和波峰焊焊接相比,一般使用较少量的波峰焊助焊剂(wave flux)和锡棒(solder bar);但是有些选择性焊接的设备需要往pot里放实心锡线(solid solder wires)而不是锡棒。

Cheers!

 

Pic & Video:Youtube

 

PS 谢谢同事Eric Bastow的分享。虽然用wave flux and solder bar少了点,影响了revenue; 但是实心锡线是比廉价的solder bar利润高出很多的产品,所以还好啦:-

光伏镀锡焊带互联条的Z-Bend (Z-Bend in tabbing ribbon soldering)

Wednesday, March 9, 2011 by Anny Zhang [Anny Zhang]

最近拜访了一个正在蓬勃发展的太阳能公司。当它的工艺工程师带我参观他们刚运行起来的太阳能模块组装工厂时(Solar Cell Module Assembling plant),向我介绍了焊接互联条(tabbing ribbon)的Z-Bend工艺。

光伏太阳能(PV, Photovoltaic )的互联条一般是镀锡铜焊带。 焊接的原理与一般SMT相似,但也不尽相同。 所用的设备就不一样。一般焊接互联带的设备统称叫做Solar Cell Tabbing String Machine (CTS).  目前太阳能公司们常用的设备有这些牌子的: Spire, Komax, Somont, Applied Materials….

Z-Bend主要是互联条在连接相邻太阳能板子的正面与反面时,设备让互联条顺着本面形成一个弯曲的角度,这样可以减缓由于互联条拉紧后对太阳能板子可能产生的压力;压力有可能损伤太阳能板子。

Z-Bend

有些公司的设备设计,可以做Z-Bend这个工艺,但是有些设备却不行。这也看太阳能板子的组装是否需要这项工艺。

现在美国这里也有越来越多的家庭在房顶上装太阳能板来发电了。光伏太阳能产业也慢慢走近民用了。

Cheers!

Solar Module on Roof

Pic:

1.      Jim Hisert withIndium Corporation

2.      Google Image

PS:

1. Z-Bend看来还是一个很新的词汇。我查了Baidu, Google, Youtube, Wikipedia, 都没有相关Z-Bend的解释链接。

2. 这个太阳能工厂从去年刚开始进行wafer production到现在的solar cell module assembling, 我前后参观了五六次了,还带了许多不同的朋友们去参观。每次都觉得很开眼界。

3. Acknowledge to: Jim Hisert with Indium Corporation  

叠成封装(Package-on-Package;PoP) 焊锡膏和助焊剂 (PoP paste and PoP flux)

Monday, February 21, 2011 by Anny Zhang [Anny Zhang]

随着电子元器件组装微型化的趋势(miniaturization),最近有越来越多的客户向我们咨询叠成封装的材料以及相关工艺(Package-on-Package;PoP)

在向客户推荐PoP材料的时候,除非客户已经十分清楚自己要什么,我们一般会和他们详细介绍叠成封装焊锡膏PoP paste 和叠成封装助焊剂PoP flux具体是什么,分析各自的优缺点,然后让客户自己做决定。

Indium 公司的PoP paste (Indium9.88HF) 用的是5号金属粉,金属比重大概在80%-83%之间,根据是有铅还是无铅而定。 我们做过一系列的实验,和常规的SMT 3号粉和4号粉,各种金属比重的焊锡膏做比较,用5号粉在这个金属比重中做出来的PoP paste,各方面的性能最好。 Indium公司的PoP flux (Indium 89HF-LV) 也是根据各种实验结果都是最好的证实后, 才推出的。 通常检测PoP焊接材料, 可以做这三个实验: Transfer Test, Wetting Test, and Electrical Test. 具体的检测方法,Indium公司的Jim Hisert在他的论文中有详细描述。《Next Generation PoP Pastes for Electronics Assembly

PoP Process

一般我个人比较喜欢推荐PoP paste,因为PoP paste能够提供extra solder。 PoP component本来就很薄,在焊接后回流的过程中十分容易“warpage 板翘”,那么component边缘部分就很有可能有一个上下之间很大的gap,导致根本无法形成良好的焊点。但是如果使用优良的PoP paste, paste中的extra solder metal 就能起到一个很好的“粘合剂”作用,即使有warage,也可以有一定的防御。 但是PoP flux在这方面就相对弱一点。

然而,PoP paste中的flux,因为要做很多功夫来清洗powder表面的氧化物,所以在回流过程中会有挺多的outgassing,这就很有可能导致空洞voiding 的产生。PoP flux相对而言,outgassing 就少很多,自然产生voiding的几率也小。

PoP paste and PoP flux

无论如何,优良的PoP paste and PoP flux,在防止wargage和voiding产生的defect方面,都是应该做得不错的。

Cheers!

 

Pic: Indium Corporation

Acknowledge to: Eric Bastow andJim Hisert with Indium Corporation