Semiconductor Packaging

Indium metal has the unique ability to cold weld (bond) to itself at room temperature. Though this is, technically, not soldering, this property makes it especially useful for low-temperature bonding applications. Back in 2008 I mentioned indium cold welding on the semiconductor packaging blog. Here are some other resources for learning more about the process:

• The official Cold Welding Application Note
• Using indium in a cryogenic seal application.
• Using indium in Flip-chip applications

Cold welding is a great solution to some really tricky bonding applications. Some nice features of using indium cold welding as a bonding method are:

1) It offers an instant attachment. Because indium will stick together upon physical contact (with a slight amount of pressure) the bonding process takes a fraction of a second as opposed to reflow soldering processes for solders or curing processes for epoxies – which can take seconds to many minutes.

2) It requires no heat. Temperature-sensitive components can be assembled without heating. The stresses that occur due to CTE (coefficient of thermal expansion) are also not an issue, which makes this a great process for attaching large dissimilar CTE materials like brittle ceramics and high expansion rate metals.

3) The bond will have exceptional thermal and electrical conductivity due to the nature of the indium that is used for this process.

You can use the indium cold welding process on any material you can successfully sputter, evaporate, reflow, or plate indium onto.

The answer to the age-old question: “What is the expected lifetime and associated strengths of an indium cold weld?” is:

The cold weld bond will last indefinitely and the bond strengths approach that of a solid piece of indium, 273 PSI.

If you have questions, please email them to askus@indium.com.

At the time of writing, the price of silver (Ag) was approaching the USD$50/tr.oz. (Troy ounce) level, and threatening to go higher. With 1 Troy ounce being 31.1grams, this makes the cost of pure silver ingot close to USD$1.60/gram.

Image from goldsilveroz.com

Materials costs are therefore a major consideration for anyone using silver in any form. Naturally, we are now seeing a few Power Semiconductor packaging houses evaluating the possibility of moving away from silver-filled epoxies for die-attach. The alternatives they are considering include the adoption of solder paste (or solder in some other form: wire / ribbon / preforms) versus a silver-filled epoxy.

Here are some thoughts on the Power Semiconductor assembly pros and cons, based on using solder paste as an alternative to silver-filled epoxies.

Good news (+)

+   Reduced materials costs
+   Improved pot-life / shelf-life *
+   Improved high temperature thermal-cycling
+   Strong, metallurgical joint formed between leadframe (substrate) / joining material / die
+   Improved thermal conductivity
+   Faster throughput (more units per hour, UPH)**
+   Easy clean-up ***
+   Does not wick onto NiPd surface to cause poor wire bondability

 * Although it is true that solder pastes are stored under refrigerated conditions, they do not require the -40C storage that is typical of silver-filled epoxies. 

 ** The dispense of solder paste is very rapid and can be done using multi-dot dispense heads. It undergoes rapid temperature reflow, versus the slow cure needed for metal-filled epoxies, which can be up to typically 1-3 hours, depending on the volume of silver epoxy.

 *** Because the solder paste flux does not cure like a polymeric material,  tubing and other conduits for the solder paste are easily cleaned out using common solvents, or can be simply purged with flux.


  ==================

Bad news (-)

-   Capital costs #
-   Adoption time / new process learning ##
-   Needs a solderable die surface
-   Voiding increase ####

 # The main cost-drivers here are:

- Reflow: Specialty reflow equipment is required for high temperature solders, such as
Heller or BTU reflow ovens

- Cleaning: If wirebonding is required after the reflow process, standard cleaning equipment and cleaning chemistry (aqueous or solvent-based) will be needed to remove flux residues

- Gas: Forming gas (H2/N2) or simple nitrogen may be needed to assist reflow.

Note that increasingly, for clip-bonding (non-wirebonding) applications using the new ultralow residue solder paste Indium9.32, even cleaning may not be needed, as the residue has been found to be compatible with compatible with a number of molding compounds in the industry.

 ## By partnering with a company like Indium Corporation with many years of experience in die-attach soldering, the ramp-up time can be significantly reduced.

 ### A solderable surface is usually a sequence of Ti / Ni / (Ag or Au) plated layers. The thickness of the silver (Ag) or gold (Au) precious metal layer is usually limited to 100nm (0.1microns). Compare this to a standard silver-epoxy bond line thickness (BLT) of 0.5-2mils (12-50microns).

 #### Acceptable voiding of less than 5% of the total die area is fairly easily achieved with good quality substrates and die-finishes.

  ==================

In closing, I am indebted to my friend and colleague Sehar Samiappan (Indium Corporation Area Technical Manager - South East Asia) for his insights.

Contact me to discuss this further.

Cheers!   Andy

I was asked this week to contribute to the upcoming IPC handbook (IPC-CH-65 HDBK) on the section on contamination and its effects on printed wiring assemblies (PWA’s). There is a clear crossover of technology from the standard SMT / PCB arena into semiconductor assembly: specifically into flip-chip, microbumps and TSV assembly. However, the terminology is “starting to collide”: phrases familiar to semiconductor manufacturers now need to be understood and become part of the lexicon of semiconductor packaging engineers coming into the field from SMT. I want to set the record straight about this, hence this blog posting, which is based on a paper I gave at the IWLPC meeting in 2009, but probably bears repeating for a wider audience.

Electrochemical Migration (ECM)

ECM is characterized by the movement of metal ions BETWEEN adjacent metal conductors, to form dendrites. The key control parameters here are:

-        Moisture or high humidity, measured as %RH

-        Presence of mobile metal ions

-        A high potential gradient, expressed in Volts per unit length (say V/cm)

High temperature may also exacerbate the problem. The hydrated metal ions, being positively charged, will migrate towards the cathode (-ve), forming a dendrite, which is a needle or tree-branch-like metal structure. The dendrite is the primary visual indicator of ECM.

Electromigration (EM)

EM, on the other hand, occurs WITHIN a metal conductor, when large numbers of high-speed electrons impact on metal atoms and dislodge them by simple momentum transfer. The major factors effecting EM are:

-        High temperature

-        Presence of mobile metal atoms

-        A high current density, expressed in Amps per unit area (say A/cm2)

It is important to note that humidity or other environmental moisture has no effect on EM, as EM occurs inside the metal joint.


The primary visual indicator of EM is the presence of voids at points in a metal interconnect near the anode (+ve), often where the current density is greatest (the “current crowding” effect - see below).
The voids are usually seen inside the joint, and can eventually lead to thermal runaway and joint failure, as the effective cross-sectional area of the joint shrinks over time, increasing the current density.

I hope this explanation is clear and makes sense.

Cheers! Andy

Low and ultralow alpha-emitting semiconductor assembly materials are now essential for flip-chip packaging and are also becoming increasingly critical for power semiconductor assembly, as smaller active device sizes and thinner wafers increase the devices' sensitivity to ionizing radiation.



An alpha particle is an ionized particle consisting of 2 neutrons and 2 protons emitted spontaneously from the nucleus of specific isotopes of certain high atomic weight  elements. Of particular interest and concern to semiconductor fabricators and packaging houses are the elements uranium (U) and thorium (Th), isotopes of which decay to give stable isotopes of lead (Pb), but which, by decaying, give rise to alpha particles.

For over a year now, we have been supplying low alpha (LA) and ultralow alpha (ULA) emitting solder pastes to Asian customers. During this time, we have faced numerous challenges: most importantly:

-        The absence of standards in the area of measurement and test methodology

-        Metrology at the ultralow alpha level is hampered by a signal to noise ratio of about 1:1, where the “noise” is simple background radiation, present at around the 0.002cph/cm2 level.

Even the definitions of the different levels are not well defined, but we are operating under the working rule that:

-        LA =< 0.020cph/cm2

-        ULA =< 0.0020cph/cm2

I had the opportunity to discuss our work at the latest Second Annual IEEE-SCV Soft Error Rate (SER) Workshop in late October this year - please follow the link to learn more -  and I’d like to thank Peng Su of Cisco for giving me the opportunity to speak at this meeting. Also look for the forthcoming (at time of writing) review paper “Challenges in Supply of Ultralow Alpha-Emitting Solder Materials” by me and Olivier Lauzeral of iROC Technologies in Chip Scale Review magazine for November/December 2010.

In the coming months, Indium Corporation will be providing LA and ULA solder alloy, preform, solder powder, solder paste and flux materials.

Cheers! Andy

Once again, here are some things I learned at this year's IWLPC show 2010 in Santa Clara. Picture below taken at Philadelphia airport, where I drafted this blog posting.

 
I think there could be ten things this time, but who’s counting? 

 

-          TSV stands for “through-silicon via”. AND “through-substrate via”. AND (as one attendee joked) “through-stuff via”. It’s also 2-3 years away from commercial implementation on anything other than camera modules: which I thought I heard last year. Hmmmm… Speaking of which…
 

-          Camera modules are still the only commercial TSV applications at the moment, although I heard arguments that camera modules were not true TSV as either they “weren’t leveraging the real potential of TSV”: simply metal-lined apertures contacting the CCD pixels on the backside of the camera die. So more like “into-silicon vias” (ISV’s) than strictly through them.
 

-          One of the major advantages of 3D stacking is heterogeneous system integration: you can put silicon, SOI, GaAs, MEMS etc all in one stack or some SiP-on-chip array and repartition the chip functionality in three dimensions exactly as you need it. You can also mix joining technologies together: coined metal bumps and ACF with diffusion bonding etc. Dr Peter Ramm of the newly renamed Fraunhofer EMFT gave a fascinating talk on the eCUBE and (new) eBRAINS projects. Peter also confessed that the eBRAINS acronym was a bit of a stretch, and I’m sure the desire for improved technology came before the acronym.
 

-          Thermal management issues for 3D (TSV-based) memory will be less of an issue than previously thought, since the driver for memory integration is reduced power consumption. That’s either 40% or 50% reduction, depending on who you talk to. Fewer RC losses = lower power wastage; less heat. Boom: you’re done. Dr Bradley McCredie of IBM pointed out in his keynote speech that by moving to TSV for DRAM, you may get a significant power saving, but this doesn’t scale: once you’ve stacked the die, that’s it. One time offer, and then as the vias get thinner – the problem starts again.
 

-          No surprise, but known good die (KGD) will be critical for chip-stacking, echoing Peter Ramm’s comments about testing for KGD. Unfortunately there are two issues here: 1/ (from Peter Ramm) that test pads will need to be integrated into the design, consuming real-estate that you thought you just won back 2/ That via-middle or via-last technology TSV will put added stresses on die that WERE KGD, up to the point that you put holes in them.
 

-          The new paradigm for consumer devices is clearly “mobility, customizability and cooooolness (MCC)”. Sorry to seem preachy here, but I heard one marketing expert, and even one engineer trot out the old adage of “smaller / cheaper / faster” (SCF), which I hoped had died out around the end of the last century. The lesson from Apple’s iPAD (at time of writing reportedly selling 1-2million units a month)  seems clear: consumers will pay for MCC no matter what. So how’s that SCF mantra working out for ya? The iPAD is much bigger than a cellphone; it’s priced at top dollar and is (arguably) not as functional as a laptop. SCF is rapidly becoming the Holy Roman Empire of marketing jibber-jabber. Ok: I think I’ve made my point: tell me what you think.
 

-          As I said during the final WLP session I never thought I’d hear the words “Intel, wirebond and leadframe” used in the same sentence. Well, that was simply showing the depths of my ignorance. Dr Saeed Shojaie from Intel’s NAND Solutions Group in Fulsom, CA and his team have been working with PTI, using mixed diameter gold wire bonds (thus eliminating wire sweep) to allow stacking of 8 die or more on a leadframe:  then mounting that stack-up inside something that looks awfully like a gull-wing LSOP (large scale outline package). OK: it IS a gull-wing LSOP. But it’s Intel, so it’s not your grandfather’s LSOP. They have done some interesting work on double-bends (“downset”) of the leads to eliminate distortion of the very delicate leadframe and still maintain the desired lead length.. Ok, you cry “Why not a TSV? They’re so cool!! “ Well, when you understand that this is Intel’s answer to solid state drives (SSD) based on reduced cost; shorter time to market; leveraging existing JEDEC package designs and test infrastucture; known reliability issues…. you realize that it is actually extremely cool, very pragmatic and a perfect example of perfecting a known form, rather than waiting for the next new thing to be half-ready. I’ve got to confess: I saw something similar stacked, one on top of the other (using PoP paste), by an Asian customer and thought it was a joke. It’s not. Saeed told us his team was going to be using 8 stacked 4GB die initially, moving to 8GB by next year. PoP stack two of these and that makes 128GB (0.128TB) of solid state drive. Nice! How about the access speed, though?
 

-          Implementation of 0.3mm WLP (wafer level packaging) is two years away… and always will be. Here’s the background: Jan Vardaman of TechSearch International took a novel approach to her chairmanship of a panel of industry luminaries discussing the future of WLP. She gave a homework preassignment to her four experts (from Broadcom, Qualcomm, Casio and National Semiconductor). There were a lot of common themes in their responses, and the general agreement was that it looks like 0.3mm WLP is easily feasible and has been for years, but it’s the substrate guys who can not reduce the routing costs to make 0.3mm feasible for portable applications. There may be 0.32 or 0.35mm as interim measures for mobile consumer applications, however, but that could be the limit based on costs.
 

-          Rosalia Beica of Applied Materials gave the closing speech, talking about the work done by the EMC-3D group. Basically, the EMC-3D group has the technology and Applied has the tools to copper-fill diffusion-barrier-layer-coated 20:1 aspect ratio silicon apertures (20microns deep, for the record), eliminating issues with voiding and overburden. Now the question is: will copper be the conductive via-fill material of choice? Thermal cycling does seem to put a lot of stress inside the vias from the modeling work I’ve seen. Let’s see how this pads out.
 

-         No news that wafer-thinning will be critical for wafer-stacking, but we heard from Bill Crouch of Süss Microtec that current minimum die thicknesses are 10microns for logic, 40microns for DRAM and 25microns for flash. The critical yield issue for thinned wafers remains debonding at the wafer edges without cracking, with the key being the physical properties of the temporary waferbonding adhesive.
 

-          Finally: too many pennants and “you look like a Russian General” as one wag told me. He’s right. Actually I’m not sure “pennant” is the correct name for those sticky “badges of honor” that the SMTA puts on the bottom of your lanyard name badge, but yes, I did look a bit of a pillock [see picture below].

Quick reminder: Device-in-skull is one year closer - the technology is already appearing.

Cheers! See you all next year.   Andy

In the surface mount technology (SMT) electronics and semiconductor packaging industries, Indium Corporation has a reputation for offering custom solutions.  In the world of solar cell manufacturing, I hope that same status is obvious.  I feel custom solutions are even MORE important in emerging technology fields like CIGS cell manufacturing.  Being the leading global supplier of indium (the metal), and a supplier of unique solder alloy shape/size/tolerance forms, we are well equipped to offer you evaporation sources that are tailored to your application.  Sure, we can supply round shot, teardrop shot, wire, ingot, preforms, and various other bulk forms of solder to keep your evaporation chamber filled.  Did you know we can also make custom solder castings to fit your particular crucible?  The process is easy, let us know if you are interested!

(Just click here to get started)

Those of you have been watching this blog for a while will know that I’ve been keeping tabs on the status of the European ELV (End-of-life vehicle) legislation on lead (Pb), mercury (Hg), cadmium (Cd) and hexavalent chromium (Cr^VI). It’s been both galling and heartening at the same time, to find that when I Google “elv legislation”, this (my) blog keeps coming up as one of the top 10 sources on the subject. OK: enough of the bloggy, solipsistic prevarication...

My friend, Geert Willems of IMEC late last week let me know that the EC (European Commission) had given its final decisions on Annex II ("the exceptions"), and pretty much adopted the recommendations of the Öko Institute from their 127 page report of September last year (2009). I have to say my hat is off to Dr. Otmar Deubzer of IZM and Stéphanie Zangl of Öko for the very thorough and logical background to this legislation.

The decisions that affect those of us in the semiconductor (flip-chip) and power semiconductor arena are primarily the ones on lead (Pb) in solders, that were formerly covered by section 8.a/ and 8.b/ of the old, outdated Annex II to Directive 2000/53/EC, and are now covered by this new legislation.

A quick visual summary of the legislation relevant to lead (Pb) in electrical interconnects is given below, and please consult the original document for confirmation, as I may have missed some subtlety of the legalese in my quest for brevity. Also, frankly, subsection 8 (b) led to some Transatlantic confusion over whether finishes on pin connectors and PWB's were covered(?), but I think the below is correct:




Refer to the table below for the timeline for of each subsection/exception:



Note that the last review of exemptions was carried out in 2009, with potential effect by 1/1/2011. This implies that the legislative hammer will potentially fall on each of those usages slated for future review on January 1st two years after the review year. Lead (Pb) for most electronics attach usages of interest to those of us in semiconductor and power semiconductor packaging may therefore be "legislated out" by 1/1/2016.

Basically, the use of Pb-containing solders in solder paste, die-attach paste, die-attach wire, solder preforms, and thermal interface materials (TIMs) in automotive electronics assembly is safe for now, and changes will not be forced on the automotive electronics assembly industry at a time when even current manufacturing practises may be leading to still-unresolved safety incidents.

Cheers!  Andy

I caught up with Alan Rae after a recent IWLPC committee meeting, where he jokingly asked me to, “Stop asking important questions” - LOL! He was kind enough to give me a few moments of his time to share his wit and wisdom, and answer some technology questions that, yes, I thought were kind of important…

[Andy Mackie] You’re increasingly being seen as “Dr Nano” by the electronics industry – how did you arrive as the focus of so much of this technology?

[Alan Rae] At the start of my career I was in the structural ceramics business. In the days of “ceramic fever” in the 1980’s the mantra was sub-micron and monosize (monodisperse) for lower temperature processing and better properties. It worked. Then at TAM Ceramics we made “sub-micron” barium titanate and other ceramic materials but we didn’t call it nano then. When I was at Cookson Electronics in the early 2000’s we started to see nanotechnology emerging from the woodwork with people saying the same about nanomaterials for the electronics industry. Then I joined NanoDynamics in 2004 and realized the scope and potential, ranging from semiconductors to touch screens to printable electronics, to LED lighting, to solar power, to materials such as nano solders, dielectrics, conductors…the list is growing but the leitmotiv is the same – small, monosize, tightly-controlled. 

[Andy Mackie] OK, so Nanotechnology has been a buzzword for quite a while – is there a clear definition yet, and what current uses are there for nanotechnologies that may not be immediately obvious?

[Alan Rae] Well, the definition has been really tough to derive – ISO TC 229 “Nanotechnologies” came up with a definition that one dimension of a particle, needle or plate should be less than 100nm but it’s really tough to define…should all particles be less than 100 nm? 50%? Any? And should it be exactly 100nm? There are a lot of opinions. The Woodrow Wilson Institute lists over 800 consumer products containing nanomaterials on the market now – industrially the products range from semiconductors, to fillers in packaging materials and underfills, to antimicrobial and self-cleaning coatings for phones. Solar panels, especially thin film ones, depend on nanomaterials in their manufacture.

[Andy Mackie] What is in the pipeline for nanotech electronics and semiconductor interconnect materials? I know that nanosolders are starting to gain ground in some areas – what else is upcoming?

[Alan Rae] Much of the work in nano metals is being done by universities and small companies – for example my small company is working with Purdue and the Air Force to develop a novel solder technology – but commercialization will come by partnering with established companies like Indium Corporation, who have the distribution and technical support so that customers will be comfortable with a new material. Cost and reliability are king. Indium is already in the reactive nano foil business; there are existing and near-term applications for silver, silver-coated copper, alumina coated boron nitride and their combinations in adhesives, shielding materials and thermal interface materials.

[Andy Mackie] Several years ago, quantum dots were being promulgated for tunable band-gap detectors and quantum computers. How close are quantum dots to seeing real uses, and what else is on the horizon?

[Alan Rae] Quantum dots are unique and have great potential in medical imaging and as frequency shifters for LEDs. The markets haven’t developed yet because of the cost and because some of the best dots are cadmium (toxic metal) based. I’m working with a group at University of Buffalo which has a silicon quantum dot process that looks like a promising alternative. Quantum dots will have their time…but not just yet. In terms of new developments – they range from core shell and modulated structures for thermoelectric to replacing indium tin oxide with carbon nanotubes or graphene. The US National Nanotechnology Initiative tracked $1.6 billion in Government spending (check out www.nano.gov) in the last year at Universities and small businesses and NSF has set up centers of excellence at Cornell and other great universities that are really working hard to translate science into technology so we can make practical products.

=======

Alan, many thanks for your time, and for sharing your insights with us.

Cheers!  Andy

At some point we have all had experiences which convinced us that metals have a high thermal conductivity. It may have been the hot spoon you left in your coffee after stirring in a little cream and sugar, or the hot door handle you grabbed on a simmering hot summer day when climbing into that now-vintage car of yours. In fact, the high thermal conductivity of metal can even account for the ability to get your tongue stuck to a metal pole in the cold of winter (or the metal screen door while waiting for the school bus as was my childhood experience). We generally understand the phenomena of metals to have a high thermal conductivity to be true, however what is the basic science behind the high thermal conductivity of metal?

In the July/August issue of Advancing Microelectronics, Dave Saums, Bob Jarrett, Andy Mackie, and Jordan Ross published an article titled, “Thermal Management Materials Choices for Power Semiconductors,” which begins to explain this.   


 

The article describes metal generically as positive ions within a “communal sea of their valence electrons”, together providing a net neutral charge.  The image above depicts this arrangement.   A metal is unique because unlike non-metallics which are viewed as highly organized lattices, valence electrons of metal atoms are not strongly held by the nucleus and are highly mobile. These mobile electrons transfer electric charge as well as heat across the metallic structure.  This freedom of the valence electrons accounts for the high thermal conductivity in metals.  At ambient temperatures, metals are attributed with high conductance, however an additional rise in thermal conductivity is found as environmental temperatures rise.  This activity can be explained using the principles explained in the Wiedemann-Franz Law.  

In electronics packaging, there are many materials to choose from which will provide various thermal dissipation outcomes. Metallic materials are generally preferred for high power devices due to their high thermal conductivity, lending them for adoption in heat sinks, heat spreaders, baseplates, and even thermal interface materials as Indium is most familiar with.  

I have been asked on numerous occasions to calculate the potential for galvanic corrosion between metals. Most times, when I am approached with this, the concern stems from an application in which the bonding metals will be mated in a corrosive environment, such as a salt solution.

When the potential is to be calculated for two elemental metals bonding, the potential for galvanic corrosion is simple to calculate. Simply look up the anodic potential difference between the two metals under the galvanic series in a general chemistry handbook and if the value is less than 0.15V (the maximum recommended for a salt solution), galvanic corrosion should not be a concern. For normal environments, such as storage in warehouses or non-temperature and humidity controlled environments there should not be more than 0.25 V difference in the Anodic Index. For controlled environments, such that are temperature and humidity controlled, 0.50 V can be tolerated. 

This value is much more difficult to calculate, however if the bonding metals are alloys rather than elemental metals. 

For instance, I cannot easily supply the anodic potential difference between 80Au20Sn and a pure Au plating to prove that it is less that 0.15V. This is because I cannot calculate the anodic potential theoretically for the AuSn alloy. Data is readily available for pure metals, but the potential for individual solder alloys must be determined experimentally because the voltage potential is not linear and as you begin to add a second metal to a pure metal, the rate of voltage change is different between different alloys. 

For this exact situation, I can speak practically however. We have tested gold plated Kovar lids for corrosion that were sealed to semiconductor packages that had a gold seal ring using a preform of AuSn. They were tested for corrosion in a salt spray chamber per MIL STD 883. Corrosion, when it occurred, always was on the lid where the porous gold allowed underlying nickel corrosion. There was never an instance of corrosion at the Au/Sn and Au interface region.

Andy Mackie: What role does gold play in protecting surfaces in SMT and semiconductor assembly processes?

Lenora Toscano: Gold does not form an oxide; it protects the nickel from oxidation or passivation. A clean nickel surface has very high solderability for most solder types, but its oxide is very difficult to remove with standard flux types. Also, gold dissolves almost instantaneously into most solders during assembly, thus promoting superior wettability.

Andy Mackie: What standards exist on the thickness of gold for different electronics and semiconductor assembly applications?

Lenora Toscano: The main application of ENIG (electroless nickel/immersion gold) coating is in chip-on-board (COB) technology, the typical thickness of the immersion gold layer on the HDI substrate being 3-5 micro-inches.

Edge connectors typically require the use of hard gold. Acid gold deposits are used for compliance with MIL-STD-275, which states that gold shall be in accordance with MIL-G-45204, Type II, Class 1. The thickness shall be 50-100 micro-inches, typical thickness is 30-50 micro-inches on 150micro-inches nickel.

On the other hand, for solderable surfaces, typical thickness is 5-15 micro-inches on 150micro-inches nickel.

For wire bonding, in general, gold plating of a minimum of 30 micro-inches on 200 micro-inches nickel works well. Soft gold is generally preferred. Soft gold processes are also used for boards designed for semiconductor chip (die) attachment. These qualities comply with Type I and III of MIL-G-45204.

Andy Mackie:  What are the differences between gold layers deposited by immersion gold and electroplated gold processes?

Lenora Toscano: There are five main differences:

1. The coating thickness is different. Immersion gold is a displacement reaction, gold displaces the nickel on the surface, and is self-limiting as the nickel surface is coated with the immersion gold. Common baths cannot produce thicknesses of much more than 10 micro-inches, while with electroplated gold the thickness depends on current and time. The higher current or longer the plating time the thicker the gold coating.
2. The structure of the gold deposit layers is different. Electroplated gold is denser that the naturally porous immersion deposit.
3. The hardness is usually different. Electroplated gold often has other metals introduced into the plating that make the deposit harder.
4. Porosity is different. Immersion deposits have more porosity that electroplated deposits; it is the nature of the plating system.
5. Deposition composition (purity) varies with additives in the bath. Immersion gold baths contain gold as the only plated metal, while electroplating systems may introduce small amounts of other metals.

Andy Mackie: How thick does gold have to be to fully protect the underlying surface, and what are the trade-offs as customers attempt to reduce their gold costs?

Lenora Toscano: Per IPC-4552 ENIG specification, 1.97 micro-inches is the recommended minimum at +/-4 sigma from the mean, with 3 – 5 micro-inches being typical.

The immersion gold deposit is porous by definition. It does offer very good protection to the underlying nickel, but over time the porosity of the deposit results in the passivation of the nickel surface and the wetting forces will be reduced. Of course, this process should take years to occur, but if the gold coating is too thin (below the minimum requirement), it will occur sooner and affect the solderability. 

Andy Mackie: What advantage does gold have over silver or other metals?

Lenora Toscano: Again, gold has good tarnish resistance and solderability after storage because it does not form an oxide or hydroxides, so it is unaffected by temperature and storage conditions that might reduce the shelf-life of the other finishes. It meets requirements for lead-free (Pb-free) assembly while offering a coplanar surface that is both solderable and aluminum-wire and gold-wire bondable.

Gold has good electrical conductivity, and produces a contact surface with low electrical resistance. Electroplated gold is also an excellent etch resist.

Electroplated silver is not widely used in the printed circuit industry. Under certain conditions or electrical potential and humidity, silver will migrate along the surface of the deposit and through the body of insulation to produce low-resistance leakage paths. Alkaline cyanide baths for silver electroplating are highly toxic.

Immersion silver is susceptible to problems if not correctly stored and even packaged. Packaging materials that contain sulfur or allow exposure to air will result in tarnishing of the surface (sulfide, sulfate, and chloride formation). High levels of surface contamination can detrimentally affect solderability.

Materials to be used in packaging of high power semiconductor devices are often chosen by their coefficient of thermal expansion, or CTE. For instance, substrates such as AlSiC, Molybdenum, and Tungsten are chosen to mimic the coefficient of thermal expansion (CTE) values of the materials they will be attached to so as they expand and contract, the substrates do so in tandem, minimizing the mechanical stresses at the interfaces between these areas, or their CTE mismatch.

The coefficient of thermal expansion (CTE) of indium does not match many materials, yet it is chosen commonly as a solder thermal interface material between substrates with as dissimilar substrate properties as silicon and copper. 

How can indium bond together silicon with a CTE of 2.6PPM/ºC and copper with a CTE of approximately 17 PPM/ºC, then undergo years of thermal and power cycling, and not show degradation of thermal performance?

The answer is in the strength and malleability of indium. Indium is the softest metal which is stable in air. Although the CTE of indium is 29 PPM/ºC, the tensile strength of indium is 273PSI, which is very soft, and the shear strength of indium is 890PSI, which is significantly higher. In an application where indium is soldered to a back-side metallized die and a copper integrated heat spreader, there is significant CTE mismatch. 

However, assuming the interfaces of these solder joints is sound with minimal voids, the bulk indium will bend and stretch along with the contraction of substrates and will not crack.        

Solder Basics...  If I needed to pick my favorite flux for hand soldering, it would easily be PoP Flux 030B.  I know it’s probably never going to find itself in household soldering toolkits, it’s a semiconductor packaging material – most people never need that good of a flux around the house, but I said it was my favorite, not the most practical. 

This is why PoP Flux 030B is the best choice around the house:

1) It has proven it’s solderability to ENIG, silver, oxidized copper, OSP, and nickel with Pb free and Sn/Pb alloys (which I’d choose any day for my personal soldering applications).

2) It is a halogen free, no-clean flux, so you can just leave it on the pipes, connectors, or stereo wires you’re connecting.

3) It is safe to use even if it isn’t completely heated and cured – this is rare for a no-clean flux.

4) The airless packaging process gives it a unique tack/viscosity ratio and a smooth texture that you just don’t get with cheapo off-the-store-shelf fluxes.

5) It activates at a relatively low temperature but can endure ~300degC reflow.  Hand soldering is not accurate, so I like the widened process window.

6) I think it’s pretty cool to use such an advanced flux for low-tech soldering, it’s overkill at its finest.

 This is a rare photo taken in the underground Structural Solder Joint Test Facility (SSJTF) nearly 5 miles below a small farming town in Central NY.  The light that you see is not really just a cellar window…

Image Courtesy of baselle.savingadvice.com/

The assembly materials and assembly techniques used in semiconductor packaging have been adopted for solar assembly, especially back end assembly.  

李宁成博士Dr. Ning-Cheng Lee

今天，有幸约到公司的在行业中的全球活招牌---李宁成博士(Dr. Ning-Cheng Lee)---吃个便饭，请教了他对行业动向的一些看法。

1．09年SMT行业的大趋势？

李：（笑"你这个topic很大噢"）主要还是component方面的变化，从2D package 转向 3D package，像盖楼房一样。以前die小，package大；那就在package上下功夫。现在已经是CSP(chip scale package)了，package已经缩小到和die一样了，无法再缩了，那么要继续微型化，就只能3D了，也只有这样可以有更好更快的电子产品。所以PoP (package on package,叠层封装) and 3D die stacking会越来越流行。 

2．基于这个大趋势，SMT行业技术方面的动向，以及其带来的挑战？

李：目前die stacking 主要涉及的是memory die, 因此还没有对散热问题带来挑战。但是以后的micro-processer，除了减小尺寸来增加transistor的个数, 另外一个途径就是stack the die 从而达到微型化的(miniaturization)。  叠了4到5层，micro-processer的个数增加了，功率增加了，散热和可靠性是一个主要的挑战。 

3．最近有许多文章都在讨论SMT工厂兼做太阳能光伏组装（Solar Cell Assembling）的后道工序。您是如何看待的？这会有什么挑战吗？

李：目前应该不会有什么大的挑战。需要解决的技术问题， SMT行业和半导体(Semiconductor)方面，有很多经验/技术是相似的；半导体行业的许多经验，以前都已经转用到SMT行业了。类似的，太阳能光伏组装也可以借鉴这些SMT的经验。这可以协助太阳能行业更好地做到low cost的流程，从而达到grid parity（太阳能电网性价比）。不过至今，似乎还没有SMT厂商在做太阳能光伏组装。我们还是拭目以待吧。

PS: 哈哈，这顿饭除了有一如既往的"听君一席话，胜读十年书"之感，还真的是免费午餐哦。"家事国事天下事，事事关心"；目光炯据，思想深邃的李博士，常常在我叽叽喳喳地说完一些社会现象和个人看法后，能一语中的地指出其本质或是深层次的含义。俗话说"小人谈人，中人谈事，高人谈哲学"；我是小人或中人，谈人又谈事；李博士是高人，能一针见血地指出其中的内涵。看来姜还是老的辣！感谢李博士！

Pic: Indium Corporation

Fans of the Semiconductor Packaging Blog will realize that marketing charts are a strange sight on this blog.  However, I thought I would share something that I found in a recent report from the Semiconductor Industry Association - because everyone is looking for some good news in light of the current economy.

I don’t like making decisions based on one or two data points, but seeing the start of a positive trend for semiconductor revenue brightened my day a little bit.  I’m glad that the chart includes the “Crash of 2000” to put things in perspective.  Young guys like me were still in college when that panic was upon us.

It’s no secret that I love WS3622.  The water soluble flux is a magic bullet for all types of semiconductor packaging applications.  As a tech guy, you need to be able to trust a flux – I trust this one.  It can be used for flip-chip attachment, sphere mounting, wafer-level bumping, and a variety of odd jobs. 

Since I began describing the flux to coworkers and customers, I have always mentioned that it is red and it has the appearance of ketchup.  Without going into my [over]use of ketchup, I guess that description stuck because it’s another material that is near and dear to my heart. 

Today I noticed that WS3622 really bares more of a resemblance to red acrylic paint.  I think it’s the smooth texture of the flux that really makes its consistency more like acrylic paint than ketchup.

I’ve always thought that the “nickel felt applicator” needs some explaining.  …And a picture.  …Heck, why not just get a video of the darn thing in action – right?  Well, that’s what we did.  The tool is used in various manual soldering operations, and appears on documents such as our “Bonding Non-Metallic Materials Using Indium and High Indium Alloys” application note.  After years of explaining what a nickel felt applicator is; now we can show you how it works too.

Basically, the nickel felt applicator is like a finger sized solder “broom”.  (For lack of a better term.)  It is used to push an alloy across a surface to spread the alloy out.  In the video shown here, it is spreading pure indium onto a metallized silicon wafer, heated to 200°C.  (I had to make this somewhat semiconductor packaging related.)   You’ll also notice the solder is quite oxidized.  It is actually the scrap material from the picture I took for an old blog entry over a year ago.  It has gotten a lot of use since then, and it has developed its fair share of dross too.

My favorite part about the nickel felt applicator is that after you are done using it, the leftover alloy is easily peeled off of the applicator.  No heat is needed.  The applicator is generally supplied with a layer of indium already attached, so be sure to strip off the indium if you're planning on using a different alloy.