Semiconductor / Power Semiconductor Assembly

Maria Durham, Indium’s new Technical Specialist in Semiconductor and Advanced Assembly Materials, has been doing some research on indium lead (In/Pb) solder alloys. We chatted about her findings this week. 

 [Andy C. Mackie: ACM] Which indium/lead solder alloys are most common, and what are their properties?

[Maria Durham: MD] Firstly, the use of lead-(Pb-)containing solders in some soldering applications is restricted due to local environmental and RoHS compliance, but there are still many applications where they are  allowed. Many military, aerospace, and industrial equipment uses, as well as many applications related to vehicles, are exempt. The table below shows the most common indium/lead (In/Pb) alloys (pink) and their properties, sorted by liquidus temperature; the higher of the two melting points (solidus and liquidus) seen for non-eutectic alloys. In blue are three comparison materials.

Indalloy 205 is the most commonly used, probably because it has the closest liquidus temperature to the tin/lead eutectic (183°C), 63Sn/37Pb (Indalloy 106). This means it can be reflowed using a standard Sn/Pb eutectic profile. The next most common alloys that are used are Indalloy7, 204, and 206.  Besides the melting range, indium has comparable thermal and electrical conductivity to standard materials.

[ACM] What makes indium-lead (In/Pb) solders so attractive, and why have we seen a recent resurgence in their usage?

 [MD] One main attraction to using indium/lead (In/Pb) solder alloys in soldering to precious metal surfaces is that, unlike tin-containing solders, they do not leach gold. That is, gold does not dissolve in them to any appreciable extent. During discussions at Semicon West in 2011, one of our California customers reported going through 8 simulated reflows with Indalloy 205 in contact with a gold surface with no loss of joint strength and no joint embrittlement. That is pretty impressive. Note that embrittlement is often caused by gold-intermetallic formation. It has been noted that even at 250°C, 50In/50Pb dissolves Au at a rate 13 times slower than it does into 63Sn/37Pb, although this, of course, is a kinetic, not a solubility limit, study.

The higher melting Indalloy 164 (92.5Pb/5In/2.5Ag) has the lowest coefficient of thermal expansion (CTE) of all of the In/Pb solders and is able to withstand the higher temperature excursions that can be seen in step-soldering type applications (where a very high melting solder is used to form the first joint, followed by a next lowest melting alloy, and so on). This is seen in applications such as power electronics assembly, where the first step solder is often used for die-attach either as a solder paste, wire, or preform. The high melting point helps the solder withstand the operational temperatures associated with under-the-hood electronics, in applications such as engine control modules, where Indalloy 151 (92.5Pb/5Sn/2.5Ag) or Indalloy 163 (95.5Pb/2Sn/2.5Ag) are most commonly used. In/Pb solder is excellent on very rigid structures such as ceramic-to-metal or ceramic-to-ceramic. The desired solidus / liquidus temperature range can be adjusted by changing the indium:lead ratio, making it very easy to “dial in” the alloy to a specific reflow process.

Another attraction to using In/Pb solders is that they exhibit good fatigue resistance in thermal cycling from -55°C to 125°C.  In testing, the 50In50Pb solder joint fatigue life is about 100 times greater than that for 63Sn/37Pb.

 [ACM] What fluxes are used in these applications, and how are they formulated differently?

 [MD] The fluxes most compatible with the lower melting point (<200°C) indium-containing solders are NC-SMQ-80 (solder paste) or the lower-tack TacFlux® 012 (suitable for use with wire, preforms, and spheres). These are no-clean fluxes, specifically formulated for lower temperature reflow.  Under appropriate low temperature reflow these fluxes leave behind benign residues that do not need to be cleaned off (“no-clean” flux), although they are often cleaned off in most practical applications, usually to ensure reliable wirebonds absent of flux spatter.

 To learn more, please contact us.

 Cheers!  Andy

The iMAPS Automotive 2012 steering committee would like to invite you to participate in the 2012 conference (May 22-23, 2012) to be held in Dearborn, Michigan. This biannual event will feature presentations in the areas of:

- Materials

- Design

- Systems and Applications

We are looking for papers from anyone involved with the automotive electronics, power semiconductor, power electronics, LED, sensor, MEMS, thermal or display industries, and any materials, substrate or equipment companies with involvement in transportation and knowledge to share.

Location: The Dearborn Inn

20301 Oakwood Boulevard

Dearborn, Michigan 48124

Submit abstracts by March 9th, please! With the renaissance of the US Automotive industry, this promises to be a major event.

I'm also hoping we will see the Automotive Electronics Council re-emerge and put the American spin on lead-free (Pb-free) electronics in automotive in the way that the Europeans have been taking on the task in the DA5.

Cheers!   Andy

PS: Contact me with any questions. I am glad to help.

Yes, here in the central New York (CNY) region, a lot of state-funded activity is beginning to bud, even in the middle of a New York winter. Local academics have been busy. Professor Wolf Yeigh, President of State University of New York Institute of Technology at Utica/Rome (SUNY-IT) recently commented on his team's plans for academic excellence in nanotechnology and semiconductors:

"The projected Computer Chip Commercialization Center (Quad-C) and Center for Advanced Technology (CAT) complex will be on the main campus of SUNYIT. Construction will begin this year, and we envision that the complex will be 120,000 ft² of lab and office spaces complemented by up to 30,000 ft2 of clean room for Quad-C. The academic CAT building will be around 65,000 ft2 of academic and research space. The two buildings will be connected by a rotunda collaboratorium, and the entire complex layout will be similar to what you'd see at the Center for Nanoscale Science and Engineering (CNSE) in Albany, allowing a free flow of academic and industry R&D interaction along with the standard teaching and learning spaces.

Rather than duplicating fundamental research done at CNSE, our facility will emphasize further application and integration of nanotechnology research and development, including testing and evaluation. The academic departments at SUNYIT, working in conjunction with CNSE faculty, will offer courses and programs in nanotechnology applied to semiconductors, materials, informatics, biology and engineering (electrical, computer, civil, mechanical, bio, and materials).

Our major connectivity within the NY school system will be with CNSE. We will also work with community colleges and private institutions in the regions just as CNSE works with community colleges and institutions in the Capital Region and beyond."

The not-for-profit Mohawk Valley (MV) Edge group has been actively promoting the area as suitable for development, with control over 400 acres of land leased from NY State adjacent to the SUNY-IT facility in Marcy. Despite the fact that several years ago, the MV Edge failed in its bid to have AMD (now Global Foundries) locate their fab in Marcy, the region still stands ready to host a manufacturing facility. Already appropriately zoned and wetland permit-approved, with all new infrastructure ideal for a semiconductor fab or similar high-technology facility, the area may be ideally suited - if not for a fab - certainly for BEOL / 2.5D and 3D assembly processes, as the site is an easy drive (less than 2 hours) from the Global Foundries Saratoga Springs, and the adjacent SUNY-run CNSE facility in Albany, the New York state capital.

Local semiconductor, solar and LED-focused companies like Indium Corporation, and the first tenants in the proposed Quad-C building, Valutek and nfrastructure, will derive benefits from the close proximity of the SUNYIT facilities.

Nestled in the foothills of the Adirondack mountains (which remains the largest park in the United States), it looks like a brand new chapter may be about to be written, as the small Mohawk Valley region transforms from its old electronics moniker "RF Valley" to "Nano Valley".

Cheers!  Andy

Following on from our discussions of last time...

As you will recall from the previous post on this topic, My friend and colleague Chris Nash and I were discussing some puzzling results for low dip height found during testing of package-on-package (PoP) materials. The findings will be of interest to everyone who uses a dipping process in both SMT and flip-chip assembly.

Post II:
For greater solder paste and flux dipping heights it appears as though a linear doctor blade (back and forth) used in a dipping process running at high speed will allow dip heights close to those expected from the theoretical engineered limit, for 50 microns and greater dip height. The high speed shear-thins the flux, which has the effect of both reducing the thickness of the boundary layer, and also has the benefit of reducing the extensional (tack) viscosity, so components can be more easily released from the dip tray.

What if you want to go to lower dip depths?

As we move into the area of copper pillar flip-chip dipping, and even (we hear) some Japanese customers doing package-on-package assembly, the dip height (dip depth) can go down to as low as 10-20microns, and this where we are hearing that rotary dip trays are coming into their own. The diagram below shows a simplified version of a flux and solder paste dipping tray.


Rotary dip trays seem to have the following advantages:

- Height Setting: The dip height/depth is set using two micrometers, so is infinitely adjustable to a precise setting, although the dip height does have to be measured.

- Low Cost: They also add zero capital cost for a new dip depth setting, compared to specially-engineered dipping trays, which can be upwards of $2,000 each.

- Accuracy and Precision of Depth: From a more pragmatic viewpoint, however, the real reason for rotary trays being used with ultra-low dip heights is that the flux depth is actually measured: there is no tacit assumption of a given dip depth being correct and constant, based on the engineering of the dipping tray. As we saw last time, an error of 20 microns is possible, and with a dip height of 50 microns or less, this is a huge problem if you are using a 50 micron dip tray and assuming that you are getting exactly that dip depth.

However, rotary dip trays also have their share of potential problems compared to linear dipping systems: 

 - Larger Surface Area: Flux and solder paste may dry out faster, and a water soluble material will be more vulnerable to the humidity content of the air. It is also more wasteful of flux, since a larger surface area of flux is exposed than will ever be used, although this may also be true of some of the linear tray designs.
 
- Circular Tray: Materials will experience a higher shear rate at the outer edge than in the middle. If spun too fast, dipping materials may accumulate at the edges, thrown outwards by centripetal force.

- Lower Shear Rate: For the same flux or solder paste dip depth, the velocity of the doctor blade will be much lower with a rotary than a linear system. However, as you can see from the illustration below, for a doctor blade moving at 1/4 the speed and 1/4 the dip height, the shear rate is the same.

As always, please contact me if you need to learn any more.

Cheers!  Andy

Solder powder particle size and shape impacts the functionality of solder paste in many ways: printing/dispensing/dipping; solderballing; graping; voiding; tack and so on.

For this reason, I just spent an interesting couple of months leading a cross-industry (two solder paste suppliers and two solder paste users) group to help my old friend Brian Toleno, chair of the IPC 5-24b (Solder Paste Task Group) put the finishing touches to the final version of the J-STD-005A. The concerns were with the definitions of powder size in paste: both the distribution and the “maximum allowable particle size”. We reached a nice pan-industry consensus, which should allow the J-STD-005A to see the light of day as a published document in 2012. I also saw some recent work by colleagues on the effect of particle size on surface area. I didn’t see the derivation of this work, so I want to show you how to calculate the surface area of solder powder in a paste.

Assume solder paste at a weight loading of x%. [Note that: As the solder powder size (diameter) decreases, the metal loading is usually also decreased by 0.5% or more to compensate for the boundary layer of thixotropic flux adhering to the particle surface, but let's make the first order assumption that x is independent of particle size]. So 1 gram of solder paste contains (x/100) grams of solder metal.

If the metal has a density of r (rho), then the volume of metal (v) per gram of solder paste:

               v = x / (r * 100)

Let’s assume that the metal particles are monodispersed (i.e.: all the same diameter (d)), so the number of particles per gram of paste (n) is then simply v (total volume of metal per gram) divided by the volume of one particle (v_p).

               n = v / v_p = x / (r * 100 * (4/3) * pi * (d/2)³ )

We can now also calculate the solder powder surface area (s) per gram of paste from our knowledge of n and the surface area per solder powder particle (s_p):

               s = n * s_p = n *4 * pi * (d/2)²

It is a simple matter of algebra to show that the ratio of surface area to volume is merely an inverse of the particle radius or diameter (I’ll leave that as homework for you):

A while back, I did a little Excel numerical integration to show the effect of powder type on the population distribution, and hence how powder “type” (2,3,4,5 and so on) affects the surface area, with some assumptions thrown in about the width of the distribution. The results are shown below, and are pretty much as you would expect. As you go from type 3 to type 6, you see about a 10 fold increase in the surface area.

 9/ Pre-reflow flux or post-reflow residue?

    - Post-reflow may not be feasible

 10/ Usage affects chemistry available and choice of color:

    - Color agent concentration needs to be optimized so other properties of flux are not affected
    - Experience shows thin films of colored flux are undetectable by eye or vision systems

 11/ Addition of even small quantities of the coloring agent will affect the physical properties to some extent:

    - Rheology: Tack / viscosity / pot-life (usage life)
    - Reflow / wetting / voiding
    - Coloring agent may also affect the electrical properties (SIR/ECM) of a no-clean flux!

12/ Water-insoluble color agent can stain substrates and cause cross-contamination within the reflow oven or final cleaning system.

    - NOTE: The most effective (deeply colored) color agents are not very water soluble.

13/ Color agent must be homogeneously distributed, especially for sub-100micron pitch flip-chip and copper pillar applications.

    - Manufacturing process and QA testing methods need to be developed for each flux and color chemistry

• High thermal conductivity (33W/mK)
• Higher melting point than SAC alloys (221C)
• Low tensile stress, so suitable for large die (5800psi)
• Excellent thermal cycling properties (-55 to 125C)

1.  Preform (a specially-shaped solder piece) with TACflux® used to hold the preform and die in place
2.  Solder paste, which holds the die in place with no extra materials added 
3.  Soft solder die-attach wire, a fluxless type of solder wire, which is melted onto the substrate metallization under an inert cover gas, and the die directly mounted onto the molten solder pool, then allowed to cool.

For reasons that I will discuss in a post later this year, a common factor that is emerging in the area of copper-pillar microbump 2.5D and 3D joining, is the adoption of thermocompression (TC) bonding for flip-chip flux/microbump soldering. TC bonding is now being predominantly adopted instead of reflow. Some of you may have the same response as I got at iMAPS 2011 from one well-known expert in packaging technology. He looked askance at me when I mentioned TC bonding for flip-chip and retorted: “That’s for bonding wafers, not soldering flip-chips!”. Even good old Wikipedia (at time of writing) seems to have the same problem – basically that the industry usage of the term has moved into the packaging arena.

I spent a little time talking to people in the industry, and on Google, putting together a buyer’s guide for those of you looking at who-is-doing-what in TC bonding. This is just a prototype guide and necessarily incomplete – if I have missed your company out then I apologize, and will add it in: just give me all the details!

This post was prompted by a Korean customer, who this month asked what the limitations are for aqueous (water-based) cleaning for fluxes used in copper-pillar flip-chip applications. How low can the pitch get before aqueous cleaning becomes unfeasible / impractical?: 40microns? 20microns? 5microns?

Good question. I don’t have a definitive answer, but I do now have an industry consensus that seems to be consistent. I’ll try to answer the query in a little while, but firstly, you’ve got to ask, "What is 'aqueous' cleaning?" Is it:

-        Deionized (DI) water?

-        Water plus a surfactant?

-        Water with a saponifier?

-        Mixed phase (oil /aqueous phase)?

-        All of the above?

DI water alone may be an ideal cleaning fluid from both a reliability and a “green” perspective, but its poor wetting onto even mildly hydrophobic surfaces, high viscosity compared to many low molecular weight organic solvents, and poor solvency for many molecules used in fluxes (resins are a good example) make it a poor choice as a pure solvent. 

It is also important to distinguish between saponifiers and surfactants:

- Surfactants: Usually a nonionic surfactant: most commonly a hydrophilic polyethylene glycol moiety with a hydrophobic carbon chain attached
-  Saponifiers: Usually basic chemistry that chemically reacts with high molecular weight acids in RMA and no-clean fluxes

Adding surface-active agents (surfactants) to water will help it to wet to less hydrophilic surfaces, and so help it move into confined spaces. The advantage of a nonionic surfactant over an ionic one is two-fold; a) there are no potentially ionic residues to cause electrical problems if improperly rinsed off b) the optimum surface-wetting enhancement (so-called “CMC”) is at a much lower surfactant concentration, but note that this also makes it more difficult to rinse off completely.

The general structure of the most common nonionic surfactant is:

               CxHy-(OC₂H₄)_n-OH

On the other hand, the way the saponifier works is a simple acid/base reaction, usually using amine chemistry:

               R’R”NR’” + RCO₂H ---> R’R”NR’”H+ + RCO₂-

The purpose of the basic saponifier is to massively increase the solubility of resins in aqueous solutions, while the surfactant is simply a means of enhancing wetting onto hydrophobic surfaces. Where it gets complicated, is when you realize that the saponified resin is now also capable of acting as a surfactant.

The reason I bring this up is that for smaller pitch flip-chip applications, we are now predominantly seeing the use of small amounts of nonionic surfactants with deionized water, along with other tricks to get the aqueous solution under the chip.

I think I’ll stop there. More next time. Meanwhile, feel free to comment or to email me on this.

Cheers! Andy

At the time of writing, the price of silver (Ag) was approaching the USD$50/tr.oz. (Troy ounce) level, and threatening to go higher. With 1 Troy ounce being 31.1grams, this makes the cost of pure silver ingot close to USD$1.60/gram.

Image from goldsilveroz.com

Materials costs are therefore a major consideration for anyone using silver in any form. Naturally, we are now seeing a few Power Semiconductor packaging houses evaluating the possibility of moving away from silver-filled epoxies for die-attach. The alternatives they are considering include the adoption of solder paste (or solder in some other form: wire / ribbon / preforms) versus a silver-filled epoxy.

Here are some thoughts on the Power Semiconductor assembly pros and cons, based on using solder paste as an alternative to silver-filled epoxies.

Good news (+)

+   Reduced materials costs
+   Improved pot-life / shelf-life *
+   Improved high temperature thermal-cycling
+   Strong, metallurgical joint formed between leadframe (substrate) / joining material / die
+   Improved thermal conductivity
+   Faster throughput (more units per hour, UPH)**
+   Easy clean-up ***
+   Does not wick onto NiPd surface to cause poor wire bondability

 * Although it is true that solder pastes are stored under refrigerated conditions, they do not require the -40C storage that is typical of silver-filled epoxies. 

 ** The dispense of solder paste is very rapid and can be done using multi-dot dispense heads. It undergoes rapid temperature reflow, versus the slow cure needed for metal-filled epoxies, which can be up to typically 1-3 hours, depending on the volume of silver epoxy.

 *** Because the solder paste flux does not cure like a polymeric material,  tubing and other conduits for the solder paste are easily cleaned out using common solvents, or can be simply purged with flux.


  ==================

Bad news (-)

-   Capital costs #
-   Adoption time / new process learning ##
-   Needs a solderable die surface
-   Voiding increase ####

 # The main cost-drivers here are:

- Reflow: Specialty reflow equipment is required for high temperature solders, such as
Heller or BTU reflow ovens

- Cleaning: If wirebonding is required after the reflow process, standard cleaning equipment and cleaning chemistry (aqueous or solvent-based) will be needed to remove flux residues

- Gas: Forming gas (H2/N2) or simple nitrogen may be needed to assist reflow.

Note that increasingly, for clip-bonding (non-wirebonding) applications using the new ultralow residue solder paste Indium9.32, even cleaning may not be needed, as the residue has been found to be compatible with compatible with a number of molding compounds in the industry.

 ## By partnering with a company like Indium Corporation with many years of experience in die-attach soldering, the ramp-up time can be significantly reduced.

 ### A solderable surface is usually a sequence of Ti / Ni / (Ag or Au) plated layers. The thickness of the silver (Ag) or gold (Au) precious metal layer is usually limited to 100nm (0.1microns). Compare this to a standard silver-epoxy bond line thickness (BLT) of 0.5-2mils (12-50microns).

 #### Acceptable voiding of less than 5% of the total die area is fairly easily achieved with good quality substrates and die-finishes.

  ==================

In closing, I am indebted to my friend and colleague Sehar Samiappan (Indium Corporation Area Technical Manager - South East Asia) for his insights.

Contact me to discuss this further.

Cheers!   Andy

I was asked this week to contribute to the upcoming IPC handbook (IPC-CH-65 HDBK) on the section on contamination and its effects on printed wiring assemblies (PWA’s). There is a clear crossover of technology from the standard SMT / PCB arena into semiconductor assembly: specifically into flip-chip, microbumps and TSV assembly. However, the terminology is “starting to collide”: phrases familiar to semiconductor manufacturers now need to be understood and become part of the lexicon of semiconductor packaging engineers coming into the field from SMT. I want to set the record straight about this, hence this blog posting, which is based on a paper I gave at the IWLPC meeting in 2009, but probably bears repeating for a wider audience.

Electrochemical Migration (ECM)

ECM is characterized by the movement of metal ions BETWEEN adjacent metal conductors, to form dendrites. The key control parameters here are:

-        Moisture or high humidity, measured as %RH

-        Presence of mobile metal ions

-        A high potential gradient, expressed in Volts per unit length (say V/cm)

High temperature may also exacerbate the problem. The hydrated metal ions, being positively charged, will migrate towards the cathode (-ve), forming a dendrite, which is a needle or tree-branch-like metal structure. The dendrite is the primary visual indicator of ECM.

Electromigration (EM)

EM, on the other hand, occurs WITHIN a metal conductor, when large numbers of high-speed electrons impact on metal atoms and dislodge them by simple momentum transfer. The major factors effecting EM are:

-        High temperature

-        Presence of mobile metal atoms

-        A high current density, expressed in Amps per unit area (say A/cm2)

It is important to note that humidity or other environmental moisture has no effect on EM, as EM occurs inside the metal joint.


The primary visual indicator of EM is the presence of voids at points in a metal interconnect near the anode (+ve), often where the current density is greatest (the “current crowding” effect - see below).
The voids are usually seen inside the joint, and can eventually lead to thermal runaway and joint failure, as the effective cross-sectional area of the joint shrinks over time, increasing the current density.

I hope this explanation is clear and makes sense.

Cheers! Andy

A quick trip to discuss roadmapping with one of the world’s top processor manufacturers, and a visit to discuss Pb-free power die-attach materials, left me with a few hours to spare at LAX.

This time around I was trying to work out how much package-on-package (PoP) solder paste we would expect to see for a waferlevel CSP (WL-CSP) or a BGA dipped to half height. The need for some deep thought was driven by a customer who asked at what point a PoP dipping paste needs to go from a type 4 to type 5, 6, 7 and so on (however you define them), based on the PoP/CSP pitch or ball diameter. Good question.

To start with, in order to get consistent quantities of paste on each sphere, the PoP paste metal loading needs to be well below the point at which rheopectic behavior can expect to be seen (that is, much less than 50% by volume of solder powder metal). By doing this, you pretty much guarantee a “monolayer” of solder paste powder particles (radius r) coating the CSP or BGA sphere (radius R). Figure 1 shows the kind of result that is typical for a good paste: in this instance our halogen-free PoP paste Indium 9.88-HF.



Figure 1: 0.4mm pitch CSP with PoP paste

If the metal loading is too high, even at time zero, you will start seeing large variations in the amount of PoP solder paste adhering to the surface of each sphere (bump), even on adjacent spheres: the small amount of paste that is picked up during the dipping process adheres to the main solder sphere in uneven clumps. This is why standard type 4 printing solder pastes just don’t work in PoP applications: not only is the particle size too big – the rheology is all wrong.

If R>>r, then a reasonable first order approximation is that you can treat the sphere surface as planar and so model the number of solder particles based on a series of hexagonally close-packed particles (Figure 2 gives the definitions).
 

Figure 2: Definitions for the PoP paste dipping process

Using the same model of solder powder particle size as in the discussion on waferbumping paste, you can calculate a couple of potentially useful things:

i/ The maximum number of solder powder particles on each solder sphere (bump)

ii/ The mass of solder paste adhering to each soldersphere

The first (i/) is useful for establishing the inherent variability due to the finite size of the solder powder, and I’m going to suggest another Mackie rule of thumb of a minimum 150 solder powder particles per solder bump, based on the maximum allowed particle size (diameter). The table below gives  the result of this rather simplistic analysis:



Table: Effect of Package Bump Diameter on Solder Paste Type Needed

A 400micron bump should therefore be fine even with a type 3 dipping paste, whereas a 200micron bump will need a type 5 paste.

I look forward to someone proving this wrong. The second (ii/) is helpful, because we can easily use it to test the theoretical mass of PoP dipping paste against what we actually find. Note that this is just simple geometry: it doesn't tell us how much paste is really needed to resolve issues such as the 60 - 90micron bowing we are hearing about from our customers, even with the more rigid PoP packages currently available.

Cheers!  Andy

This week a customer in Asia asked why one of our new epoxy fluxes was not allowing the package-on-package (PoP) device to be picked up from the dipping tray. Obviously, the vacuum nozzle must have sufficient force to extract the PoP package from the PoP flux reservoir (yellow, below).



Those of you who know me also know that I am always trying to reduce things to numbers so, naturally I got thinking about how I would model this from a physical viewpoint and came up with the following:

If the downward force (weight of component plus tack force of epoxy flux) is greater than the upward force (air pressure on the bottom of the component), then the component could not be extracted from the epoxy flux. The figure shows the different variables. Expressing this mathematically, this comes out, in SI units, as:

Downward force = m.g + n.Ft.pi.(d/2)^2

where Ft is the tack force in units of mass per unit area, taken from the maximum tack force determined by the Solder Paste Tack Test from J-STD-005, ANSI/IPC TM 650:2.4.44

Upward force = 101000.A.pi.(D/2)^2

where A is the measure (fraction) of atmospheric pressure and denotes how good the vacuum is (zero vacuum is 0.0atm : hard vacuum is 1.0atm).

There are some uncertainties with this approach: How does the vacuum vary across the nozzle diameter? Does the 5mm diameter probe used in the IPC test equate to a complex CSP (chip-scale package) bottom surface, with many rounded solder bumps or solderspheres? And so on. But, at least the model puts us in the right ballpark. Just to give you a feel for how this works, the second figure shows some results. Note that scenario (iv) is the only one showing problems (negative force balance).

The data implies that you are only likely to see an issue with inability to pick up components from a dipping flux tray if either:

• Components: Heavy (thick / large)
• Vacuum Nozzle: Too small a diameter and/or the vacuum is weak/poor
• Flux: Very tacky (high tack force)

For many of the newer applications, component sphere/bump immersion to just deeper than the bump height (say 100-110%) is desirable. If the customer dips the whole bottom of the component into a standard (non-epoxy) flux, this potentially opens up a lot of issues including reliability (SIR; electrochemical migration); component displacement (skewing) during reflow; as well as difficulty in picking up the component from the tray. The solution to this series of issues, is to choose either a standard flux with a high pre-reflow SIR, such as our PoPflux 30B, or a low-volatile content epoxy flux.

I'll have more to say on epoxy fluxes in a couple of months, as we are currently nearing the end of extensive testing at several customers in Europe and Asia.

Low and ultralow alpha-emitting semiconductor assembly materials are now essential for flip-chip packaging and are also becoming increasingly critical for power semiconductor assembly, as smaller active device sizes and thinner wafers increase the devices' sensitivity to ionizing radiation.



An alpha particle is an ionized particle consisting of 2 neutrons and 2 protons emitted spontaneously from the nucleus of specific isotopes of certain high atomic weight  elements. Of particular interest and concern to semiconductor fabricators and packaging houses are the elements uranium (U) and thorium (Th), isotopes of which decay to give stable isotopes of lead (Pb), but which, by decaying, give rise to alpha particles.

For over a year now, we have been supplying low alpha (LA) and ultralow alpha (ULA) emitting solder pastes to Asian customers. During this time, we have faced numerous challenges: most importantly:

-        The absence of standards in the area of measurement and test methodology

-        Metrology at the ultralow alpha level is hampered by a signal to noise ratio of about 1:1, where the “noise” is simple background radiation, present at around the 0.002cph/cm2 level.

Even the definitions of the different levels are not well defined, but we are operating under the working rule that:

-        LA =< 0.020cph/cm2

-        ULA =< 0.0020cph/cm2

I had the opportunity to discuss our work at the latest Second Annual IEEE-SCV Soft Error Rate (SER) Workshop in late October this year - please follow the link to learn more -  and I’d like to thank Peng Su of Cisco for giving me the opportunity to speak at this meeting. Also look for the forthcoming (at time of writing) review paper “Challenges in Supply of Ultralow Alpha-Emitting Solder Materials” by me and Olivier Lauzeral of iROC Technologies in Chip Scale Review magazine for November/December 2010.

In the coming months, Indium Corporation will be providing LA and ULA solder alloy, preform, solder powder, solder paste and flux materials.

Cheers! Andy

Once again, here are some things I learned at this year's IWLPC show 2010 in Santa Clara. Picture below taken at Philadelphia airport, where I drafted this blog posting.

 
I think there could be ten things this time, but who’s counting? 

 

-          TSV stands for “through-silicon via”. AND “through-substrate via”. AND (as one attendee joked) “through-stuff via”. It’s also 2-3 years away from commercial implementation on anything other than camera modules: which I thought I heard last year. Hmmmm… Speaking of which…
 

-          Camera modules are still the only commercial TSV applications at the moment, although I heard arguments that camera modules were not true TSV as either they “weren’t leveraging the real potential of TSV”: simply metal-lined apertures contacting the CCD pixels on the backside of the camera die. So more like “into-silicon vias” (ISV’s) than strictly through them.
 

-          One of the major advantages of 3D stacking is heterogeneous system integration: you can put silicon, SOI, GaAs, MEMS etc all in one stack or some SiP-on-chip array and repartition the chip functionality in three dimensions exactly as you need it. You can also mix joining technologies together: coined metal bumps and ACF with diffusion bonding etc. Dr Peter Ramm of the newly renamed Fraunhofer EMFT gave a fascinating talk on the eCUBE and (new) eBRAINS projects. Peter also confessed that the eBRAINS acronym was a bit of a stretch, and I’m sure the desire for improved technology came before the acronym.
 

-          Thermal management issues for 3D (TSV-based) memory will be less of an issue than previously thought, since the driver for memory integration is reduced power consumption. That’s either 40% or 50% reduction, depending on who you talk to. Fewer RC losses = lower power wastage; less heat. Boom: you’re done. Dr Bradley McCredie of IBM pointed out in his keynote speech that by moving to TSV for DRAM, you may get a significant power saving, but this doesn’t scale: once you’ve stacked the die, that’s it. One time offer, and then as the vias get thinner – the problem starts again.
 

-          No surprise, but known good die (KGD) will be critical for chip-stacking, echoing Peter Ramm’s comments about testing for KGD. Unfortunately there are two issues here: 1/ (from Peter Ramm) that test pads will need to be integrated into the design, consuming real-estate that you thought you just won back 2/ That via-middle or via-last technology TSV will put added stresses on die that WERE KGD, up to the point that you put holes in them.
 

-          The new paradigm for consumer devices is clearly “mobility, customizability and cooooolness (MCC)”. Sorry to seem preachy here, but I heard one marketing expert, and even one engineer trot out the old adage of “smaller / cheaper / faster” (SCF), which I hoped had died out around the end of the last century. The lesson from Apple’s iPAD (at time of writing reportedly selling 1-2million units a month)  seems clear: consumers will pay for MCC no matter what. So how’s that SCF mantra working out for ya? The iPAD is much bigger than a cellphone; it’s priced at top dollar and is (arguably) not as functional as a laptop. SCF is rapidly becoming the Holy Roman Empire of marketing jibber-jabber. Ok: I think I’ve made my point: tell me what you think.
 

-          As I said during the final WLP session I never thought I’d hear the words “Intel, wirebond and leadframe” used in the same sentence. Well, that was simply showing the depths of my ignorance. Dr Saeed Shojaie from Intel’s NAND Solutions Group in Fulsom, CA and his team have been working with PTI, using mixed diameter gold wire bonds (thus eliminating wire sweep) to allow stacking of 8 die or more on a leadframe:  then mounting that stack-up inside something that looks awfully like a gull-wing LSOP (large scale outline package). OK: it IS a gull-wing LSOP. But it’s Intel, so it’s not your grandfather’s LSOP. They have done some interesting work on double-bends (“downset”) of the leads to eliminate distortion of the very delicate leadframe and still maintain the desired lead length.. Ok, you cry “Why not a TSV? They’re so cool!! “ Well, when you understand that this is Intel’s answer to solid state drives (SSD) based on reduced cost; shorter time to market; leveraging existing JEDEC package designs and test infrastucture; known reliability issues…. you realize that it is actually extremely cool, very pragmatic and a perfect example of perfecting a known form, rather than waiting for the next new thing to be half-ready. I’ve got to confess: I saw something similar stacked, one on top of the other (using PoP paste), by an Asian customer and thought it was a joke. It’s not. Saeed told us his team was going to be using 8 stacked 4GB die initially, moving to 8GB by next year. PoP stack two of these and that makes 128GB (0.128TB) of solid state drive. Nice! How about the access speed, though?
 

-          Implementation of 0.3mm WLP (wafer level packaging) is two years away… and always will be. Here’s the background: Jan Vardaman of TechSearch International took a novel approach to her chairmanship of a panel of industry luminaries discussing the future of WLP. She gave a homework preassignment to her four experts (from Broadcom, Qualcomm, Casio and National Semiconductor). There were a lot of common themes in their responses, and the general agreement was that it looks like 0.3mm WLP is easily feasible and has been for years, but it’s the substrate guys who can not reduce the routing costs to make 0.3mm feasible for portable applications. There may be 0.32 or 0.35mm as interim measures for mobile consumer applications, however, but that could be the limit based on costs.
 

-          Rosalia Beica of Applied Materials gave the closing speech, talking about the work done by the EMC-3D group. Basically, the EMC-3D group has the technology and Applied has the tools to copper-fill diffusion-barrier-layer-coated 20:1 aspect ratio silicon apertures (20microns deep, for the record), eliminating issues with voiding and overburden. Now the question is: will copper be the conductive via-fill material of choice? Thermal cycling does seem to put a lot of stress inside the vias from the modeling work I’ve seen. Let’s see how this pads out.
 

-         No news that wafer-thinning will be critical for wafer-stacking, but we heard from Bill Crouch of Süss Microtec that current minimum die thicknesses are 10microns for logic, 40microns for DRAM and 25microns for flash. The critical yield issue for thinned wafers remains debonding at the wafer edges without cracking, with the key being the physical properties of the temporary waferbonding adhesive.
 

-          Finally: too many pennants and “you look like a Russian General” as one wag told me. He’s right. Actually I’m not sure “pennant” is the correct name for those sticky “badges of honor” that the SMTA puts on the bottom of your lanyard name badge, but yes, I did look a bit of a pillock [see picture below].

Quick reminder: Device-in-skull is one year closer - the technology is already appearing.

Cheers! See you all next year.   Andy

… and we’re back on the question of “how small a solder powder particle do I need, to achieve a certain bump height or bump diameter”?. There are a lot of factors that control this, but after taking the metal loading and other, second order, variables out of the picture, the two main questions to be answered are:

-          How big is the bump (width or height)?

-          What is your allowable bump height / diameter variability?

As solder bump dimensions shrink, the finite size of the particles in the solder paste used to form that bump affects the final solder bump variability. See the figure below for a visual description:

The variability therefore comes from each solder paste deposit containing a certain number of solder particles; more or less solder particles than the one next to it and so on. The question then is: how many solder particles (n), and of what diameter (d)?

Note that    n = [N(max)-N(min)] / 2

You can see the effect of this in the enclosed table:

This week's topic is both wafer bumping and substrate bumping with solder paste, and the issue of powder size. I’ve recently been dealing with some issues from customers who are concerned with the question of “how small a solder powder particle do I need, to achieve a certain bump height or bump diameter”? There are some "rules of thumb" on this in the electronics assembly industry, and I'll go into them later. In my next posting, I'll show why they may not be relevant or appropriate for the standard waferbumping process.

To begin: there are lots of ways of forming deposits of solder in a small form factor, and solder paste printing remains one of the most reliable, although yield drops dramatically at below 120microns pitch (some say 100microns).



If you are stencil printing solder paste, there are two guiding principles:

1/ Sbiroli’s Rule: The width of the stencil opening must be 7 particles or greater. By the word “particle”, we err on the side of caution and refer to the highest controlled particle diameter. For example, in the case of a type 3 paste, this will be around 45microns, although you should refer to my previous posting on the subject of powder size standardization (for types 5,6,7 and so on) and the poor state that that is in.

2/ Anglin’s Rule: You should not exceed an aperture ratio of 1.6. The aperture ratio being a measure of the aperture wall area to “open area”. As I showed in a previous post, this rule originates from boundary-layer-type considerations of release from the stencil walls by the pseudoplastic/thixotropic solder paste material. 


 

What if you are NOT stencil printing? The Flip Chip International (FCI) “drive in” process, which uses a developed photomask as a kind of “in situ” stencil for solder paste, allows for 5 or 6 print strokes using a soft squeegee to ensure that each aperture is filled. There are no problems here with stencil release, so how do we go about thinking of what particle size is required in this and similar processes? I think I have the answer: more next time.

Cheers!

Andy