Indium Corporation Blogs

When designing a Package-on-Package (PoP) assembly process, there are many variables that need to be considered in order to be successful.  While the chemistry of your PoP dipping flux or paste plays a major role in PoP assembly, there is also much to consider in terms of the components, equipment, and reflow parameters being utilized. 

In order to help illustrate these variables, I have created the following Ishikawa diagram:

While I’m sure there are some variables that I have missed, these are the main ones to consider. 

For help deciding which products are right for your PoP process or help troubleshooting your current process, please contact AskUs@indium.com.

7月份，我有幸去了景色迷人的三藩市(San Francisco)参加Semicon West展会，并听了“The 2.5 & 3 D packaging landscape for 2015 and beyond”的技术讲座。 这是我第一次参加半导体方面的展会，虽然2.5D 和3D packaging等相关词语听多了，但是真正含义是什么，也是直到最近才真正了解。 上周Triquint Semiconductor的齐权博士(Dr. Quan Qi)给我进一步讲解后，才又“豁然开朗”了许多。

简单来说吧，2.5D就是还要依靠一层Interposer来叠加，而不是直接logic & memory叠加到substrate上面。 而3D packaging 就能真正做到logic & memory到substrate上的直接多层叠加。齐博士给我举了一个很好的例子为什么现在很多公司还是在做2.5D，而不是3D,主要是3D有很大的CTE Mismatch. 比如说Logic & Memory的CTE 是3ppm, 但是substrate是17ppm。 在如此微型化的今天，很多小球（sphere）和pad就会因为CTE的大差别而错位。 如果引入了一层interposer, 就能够缓冲CTE mismatch 的问题。

 2.5D 和3D packaging各自的优劣势，存在的问题和挑战，专家们都在这个演讲稿里面有自己详细的分析，如果有兴趣，很值得阅读参考：“The 2.5 & 3 D packaging landscape for 2015 and beyond”

Indium Corporation能够为2.5D 和3D packaging提供各种Flip-Chip, Package-on-Package, 和Ball-Attach 之间的连接材料和解决方案。 欢迎参考: http://www.indium.com/products/semiconductorpackagingassembly.php

Cheers! 

Picture Resource: Dr. John Xie’s (Altera Coproration) presentation in Semicon West  2012. 

Browse the coming attractions at your local movie theater.  How many 3D movies are being advertised?  3D is a very exciting technology for movie and TV watchers, and the future of it may be based in three other 3D technologies.

Let's start with the initial building block of any electronic device, the chip.  Wikipedia describes the 3D Chip as: "a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit."   The result is a chip that is faster, smaller, and consumes less power than a single layer chip.  This is a fairly new technology that has been developed in the last five years and is still gaining popularity.

The next phase of manufacturing, and the area where we focus, is 3D Packaging.  When you stack several chips (regular or 3D) together, you are performing 3D Packaging or Package on Package (PoP) or System in Package (SiP).  This is also a fairly new technology but it is widely used.  As with the 3D chip, the goal of this technology is to provide a faster, smaller device that consumes less power.  Dr. Andy Mackie, Semiconductor Assembly Materials Product Manager here at Indium Corporation, recently blogged about his graphic representation of the complex 3D Packaging processes.  He has included the 3D and the 2.5D packaging into his chart which will be on display at Semicon West 2012.

Once you have the chips, you need a substrate to attach them to -  that is the final 3D technology.  3D MID (molded interconnect device) is a technology that has been around for about 20 years. Typical rigid substrates constrain design and are generally less adaptable to the tiny devices being designed today.  Flexible substrates open up the design possibilities with the ability to twist and turn as needed.  3D MID are made out of lighter materials (like thermoplastics) than rigid substrates and can be molded into a variety of 3D shapes.  This allows for greater design possibilities while producing a substrate that is lighter and more compact.  In automotive applications this can translate to lighter vehicles that need less fuel to operate.  Of course there are the challenges of incorporating the circuitry into the thermoplastic and then soldering to the non-flat (sometimes vertical) surfaces.  This technology will be discussed at the 10th International Congress on 3D MID Technology in Germany in September.

Like most new technologies, the many facets of 3D start off expensive and are not widely adopted.  But as new manufacturing techniques are developed to reduce cost, 3D TVs and all the 3D electronic assembly technology that may support them will become increasingly common place.

Photo from Cicor.

Carol

Following on from our discussions of last time...

As you will recall from the previous post on this topic, My friend and colleague Chris Nash and I were discussing some puzzling results for low dip height found during testing of package-on-package (PoP) materials. The findings will be of interest to everyone who uses a dipping process in both SMT and flip-chip assembly.

Post II:
For greater solder paste and flux dipping heights it appears as though a linear doctor blade (back and forth) used in a dipping process running at high speed will allow dip heights close to those expected from the theoretical engineered limit, for 50 microns and greater dip height. The high speed shear-thins the flux, which has the effect of both reducing the thickness of the boundary layer, and also has the benefit of reducing the extensional (tack) viscosity, so components can be more easily released from the dip tray.

What if you want to go to lower dip depths?

As we move into the area of copper pillar flip-chip dipping, and even (we hear) some Japanese customers doing package-on-package assembly, the dip height (dip depth) can go down to as low as 10-20microns, and this where we are hearing that rotary dip trays are coming into their own. The diagram below shows a simplified version of a flux and solder paste dipping tray.


Rotary dip trays seem to have the following advantages:

- Height Setting: The dip height/depth is set using two micrometers, so is infinitely adjustable to a precise setting, although the dip height does have to be measured.

- Low Cost: They also add zero capital cost for a new dip depth setting, compared to specially-engineered dipping trays, which can be upwards of $2,000 each.

- Accuracy and Precision of Depth: From a more pragmatic viewpoint, however, the real reason for rotary trays being used with ultra-low dip heights is that the flux depth is actually measured: there is no tacit assumption of a given dip depth being correct and constant, based on the engineering of the dipping tray. As we saw last time, an error of 20 microns is possible, and with a dip height of 50 microns or less, this is a huge problem if you are using a 50 micron dip tray and assuming that you are getting exactly that dip depth.

However, rotary dip trays also have their share of potential problems compared to linear dipping systems: 

 - Larger Surface Area: Flux and solder paste may dry out faster, and a water soluble material will be more vulnerable to the humidity content of the air. It is also more wasteful of flux, since a larger surface area of flux is exposed than will ever be used, although this may also be true of some of the linear tray designs.
 
- Circular Tray: Materials will experience a higher shear rate at the outer edge than in the middle. If spun too fast, dipping materials may accumulate at the edges, thrown outwards by centripetal force.

- Lower Shear Rate: For the same flux or solder paste dip depth, the velocity of the doctor blade will be much lower with a rotary than a linear system. However, as you can see from the illustration below, for a doctor blade moving at 1/4 the speed and 1/4 the dip height, the shear rate is the same.

As always, please contact me if you need to learn any more.

Cheers!  Andy

随着电子元器件组装微型化的趋势(miniaturization)，最近有越来越多的客户向我们咨询叠成封装的材料以及相关工艺(Package-on-Package；PoP)。

在向客户推荐PoP材料的时候，除非客户已经十分清楚自己要什么，我们一般会和他们详细介绍叠成封装焊锡膏PoP paste 和叠成封装助焊剂PoP flux具体是什么，分析各自的优缺点，然后让客户自己做决定。

Indium 公司的PoP paste (Indium9.88HF) 用的是5号金属粉，金属比重大概在80%-83%之间，根据是有铅还是无铅而定。 我们做过一系列的实验，和常规的SMT 3号粉和4号粉，各种金属比重的焊锡膏做比较，用5号粉在这个金属比重中做出来的PoP paste，各方面的性能最好。 Indium公司的PoP flux (Indium 89HF-LV) 也是根据各种实验结果都是最好的证实后， 才推出的。 通常检测PoP焊接材料， 可以做这三个实验： Transfer Test, Wetting Test, and Electrical Test. 具体的检测方法，Indium公司的Jim Hisert在他的论文中有详细描述。《Next Generation PoP Pastes for Electronics Assembly》

一般我个人比较喜欢推荐PoP paste，因为PoP paste能够提供extra solder。 PoP component本来就很薄，在焊接后回流的过程中十分容易“warpage 板翘”，那么component边缘部分就很有可能有一个上下之间很大的gap，导致根本无法形成良好的焊点。但是如果使用优良的PoP paste, paste中的extra solder metal 就能起到一个很好的“粘合剂”作用，即使有warage，也可以有一定的防御。 但是PoP flux在这方面就相对弱一点。

然而，PoP paste中的flux，因为要做很多功夫来清洗powder表面的氧化物，所以在回流过程中会有挺多的outgassing，这就很有可能导致空洞voiding 的产生。PoP flux相对而言，outgassing 就少很多，自然产生voiding的几率也小。

无论如何，优良的PoP paste and PoP flux，在防止wargage和voiding产生的defect方面，都是应该做得不错的。

Cheers!

Pic: Indium Corporation

Acknowledge to: Eric Bastow andJim Hisert with Indium Corporation  

A quick trip to discuss roadmapping with one of the world’s top processor manufacturers, and a visit to discuss Pb-free power die-attach materials, left me with a few hours to spare at LAX.

This time around I was trying to work out how much package-on-package (PoP) solder paste we would expect to see for a waferlevel CSP (WL-CSP) or a BGA dipped to half height. The need for some deep thought was driven by a customer who asked at what point a PoP dipping paste needs to go from a type 4 to type 5, 6, 7 and so on (however you define them), based on the PoP/CSP pitch or ball diameter. Good question.

To start with, in order to get consistent quantities of paste on each sphere, the PoP paste metal loading needs to be well below the point at which rheopectic behavior can expect to be seen (that is, much less than 50% by volume of solder powder metal). By doing this, you pretty much guarantee a “monolayer” of solder paste powder particles (radius r) coating the CSP or BGA sphere (radius R). Figure 1 shows the kind of result that is typical for a good paste: in this instance our halogen-free PoP paste Indium 9.88-HF.



Figure 1: 0.4mm pitch CSP with PoP paste

If the metal loading is too high, even at time zero, you will start seeing large variations in the amount of PoP solder paste adhering to the surface of each sphere (bump), even on adjacent spheres: the small amount of paste that is picked up during the dipping process adheres to the main solder sphere in uneven clumps. This is why standard type 4 printing solder pastes just don’t work in PoP applications: not only is the particle size too big – the rheology is all wrong.

If R>>r, then a reasonable first order approximation is that you can treat the sphere surface as planar and so model the number of solder particles based on a series of hexagonally close-packed particles (Figure 2 gives the definitions).
 

Figure 2: Definitions for the PoP paste dipping process

Using the same model of solder powder particle size as in the discussion on waferbumping paste, you can calculate a couple of potentially useful things:

i/ The maximum number of solder powder particles on each solder sphere (bump)

ii/ The mass of solder paste adhering to each soldersphere

The first (i/) is useful for establishing the inherent variability due to the finite size of the solder powder, and I’m going to suggest another Mackie rule of thumb of a minimum 150 solder powder particles per solder bump, based on the maximum allowed particle size (diameter). The table below gives  the result of this rather simplistic analysis:



Table: Effect of Package Bump Diameter on Solder Paste Type Needed

A 400micron bump should therefore be fine even with a type 3 dipping paste, whereas a 200micron bump will need a type 5 paste.

I look forward to someone proving this wrong. The second (ii/) is helpful, because we can easily use it to test the theoretical mass of PoP dipping paste against what we actually find. Note that this is just simple geometry: it doesn't tell us how much paste is really needed to resolve issues such as the 60 - 90micron bowing we are hearing about from our customers, even with the more rigid PoP packages currently available.

Cheers!  Andy

最近，公司在和一個原始設計商(ODM)公司談合作項目。

本來的初衷，是希望能給這傢ODM, 它的上游OEM（原始設備製造商）公司，下游EMS（製造加工廠），提供Indium公司性能穩定良好的SMT焊接材料(如錫膏solder paste，錫綫solder wires)等，並為他們提供及時的技術服務和一系列解決方案，協助他們做到最好。

但是在相互交流的過程中，我們了解到這傢公司還做IC設計，芯片曡層封裝等(Package on Package; PoP)。其實，在曡層封裝應用中，的Indium 公司也有的很成熟的半導體技術和材料。比如説for BGA/CSP的solder balls, dispensing paste/flux, transfer paste/flux, PoP paste/flux, etc. 

站在客戶端的角度，他們也應該希望有供應商能提供這一整套的解決方案，以對内外材料/技術的洞悉，幫助他們順利完成這個（些）大項目。

站在我們自己的角度，在協助客戶時，也最好有發現“交叉銷售Cross Selling”機會的眼睛， “发现销售不同产品或向不同部门（或客户）销售的机会，从而帮助客户，满足客户需求，达到销售目的。”

Cheers!

PS:  小帆這兩天在博客中寫到“操作系统的改进更新目前来讲都是小步前行。如若想像windows95/98那样革命性的变化，那就要看未来人机交互方式的变化。从某种意义上讲，硬件技术而不是软件技术将是未来变革到来的动力。比如，如果你能把电脑做成手表；如果你的输入设备能凭空展开或投射虚拟。。。”他的話語也讓我立刻想起現在電子行業的微型化(miniaturization)，芯片的曡層封裝，3D Dimension, etc. …..  科技以人爲本。很幸運，能生活在高科技的今天，享受各種高科技帶來的服務和便捷！

• Sn Whiskers - Sn whiskers are filament growth that protrudes from pure Sn surface coatings and are a result of the compressive stress inside of that Sn.  For an overview of Sn whiskers, check out the article titled Structure and Kinetics of Sn Whisker Growth on Pb-free Solder Finish.  When looking at Sn whisker mitigation, it turns out that Pb added to Sn is very effective.  That's why Sn/Pb components never show whisker growth.  There are other mitigation techniques such as Ni underplating and doping with Bi but they don't seem as effective a good old Sn/Pb.  Over time (often greater than 5 years), whiskers can grow large enough to form a short between adjacent components.  Whiskers may not be a big issue for cell phones (because of their short life) but is a major concern for military, medical, and aerospace electronics.
• Pb-Free Alloy Reliability - The two most common alloys used for Pb-Free soldering are SAC305 and SAC387.  When compared to Sn63Pb37, the SAC alloys are considerably more brittle.  This means that under low stress conditions, they actually may be more reliable than Sn/Pb.  However, under higher stress conditions, Sn/Pb can creep to absorb some of that stress while SAC alloys can simply fracture.  The reduced reliability of SAC can be seen under challenging thermal cycling and drop testing.  There are studies on doped SAC alloys that show promise in bridging the reliability gap, but more work is necessary in this area.
• Higher Reflow Temperatures - The peak reflow temperature for Sn/Pb assemblies was generally around 210-215 C.  For Pb-Free assembly, it tends to be around 240-250 C.  This increase of 30+ C can reap havoc on boards and components.  For components, higher temperatures increase their susceptibility to moisture.  The MSL levels are generally more stringent for Pb-Free.  For boards, you can get barrel cracking, delamination, and CAF growth.
• Proven Pb-Free Issues: There have been a number of reported issues that are likely related to Pb-Free.  Here are a couple: NASA and Sn whiskers; Pacemakers; X-Box RROD (Red Ring of Death)

• Recycling - As Dr. Lasky notes in his blog, there are a number of benefits to eliminating Pb from the recycling process.  Although, Pb contamination can easily be dealt with at state of the art recycling facilities, there are unfortunately too many uncontrolled reclaim situations in poor and developing countries.  The elimination of Pb makes those people safer.
• Technology Advancement - Consumer electronics are almost completely Pb-Free and have been since 2006.  Since 2006, we have seen a significant amount of advancement in the technology behind cell phones, laptop computers, and handheld GPS.  Had Pb-Free been such an impediment, there would have clearly been some stagnation in the advancement of those technologies.  In consumer electronics, there has been the implementation of 0.4 and 0.3 mm pitch CSP's, 0201's, package-on-package (PoP) to continue to improve the technologies.  Remember, the first iPhone was Pb-Free!  As the technology advances, there will always be challenges but they are not directly related to going Pb-Free.
• Whiskers (Non)Issue - It is absolutely proven that pure Sn can form whiskers that could be a long term reliability issue.  However, there are existing Pb-Free alternatives today and in many cases the standard mitigation techniques are good enough.  The real issue here is cost.  People want to use pure Sn (or as little mitigation adders as possible) to get the cheapest component.  However, if you eliminate the Sn, you can eliminate the whiskers.  Texas Instruments uses Ni/Pd/Au for many parts.  That is Pb-Free and contains no Sn.  Whisker free alternatives do exist!

Dr. Andy Mackie recently put together a model to determine the probability that a component can be successfully dipped in solder paste or flux.  Here is a little more from him on this subject:

"A customer in Asia was asking why one of our no-clean package-on-package fluxes, the ultralow residue NC510, was not allowing the PoP device to be picked up from the dipping tray. It turned out that the customer was allowing the flux to coat the whole of the bottom of the component, not just the solder bumps, so the vacuum nozzle had insufficient force to extract the PoP package from the flux . I got thinking about how I would model this from a physical viewpoint.

If the downward force (weight of component plus tack of flux) is greater than the upward force (air pressure on the bottom of the component), then the component could not be extracted from the flux. The figure shows the different variables. Expressing this mathematically, this comes out, in SI units, as:

Downward force = m.g + n.Ft.pi.(d/2)^2

where Ft is the tack force in units of mass per unit area, taken from the maximum tack force determined by the Tack Test Method from J-STD-005, ANSI/IPC TM 650:2.4.44

Upward force = 101000.A.pi.(D/2)^2

where A is the measure (fraction) of atmospheric pressure and denotes how good the vacuum is (zero vacuum is 0.0 : hard vacuum is 1.0).

There are some uncertainties with this approach: How does the vacuum vary across the nozzle diameter? Does the 5mm diameter flat IPC probe equate to a much smaller sphere? and so on, but it at least puts us in the right ballpark.
Just to give you a feel for how this works, the second figure shows some data. Note that scenario iv is the only one showing problems (negative force balance).  The data implies that you are only likely to see an issue with inability to pick up PoP components from a dipping PoP flux tray if either:

- Components: Heavy and have many large PoP solder bumps
- Vacuum Nozzle: Too small and the vacuum is weak/poor
- Flux: Very tacky (high tack force)

and certainly, if the customer dips the whole bottom of the component into the flux, this opens up a lot of issues, including reliability (SIR); component displacement during reflow; as well as inability to pick up the component from the tray. This is why we always recommend a flux dipping height of 40-50% of the PoP bump height, to eliminate these issues."

I have found this model not only interesting, but useful for technicians to use when asked why components are 'only dipped 50%'.  As a technician, it is good to have a scientific reason to refer to - even though experience may have already proven the theory to us personally. 

Indium Booth at Semicon West 2009

芯片封装

这周的7月14号到16号，在美国三藩市(San Francisco) 举行了半导体行业的美国区盛事，Semicon West 2009。 同事们回来分享，总体感觉是各个参展商们都表现得很好。Indium公司一如既往，与大家分享新产品和新科技。在Indium公司提供的各种半导体焊接材料中，前导工序晶圆制造材料（wafer mfg and process），功率半导体封装材料，叠层封装(Package on Package---PoP)材料，是我们展会中的重点。

最近又系统的看了一下，芯片封装的进展，大概分为这几个阶段/方式：一、DIP双列直插式封装。二、PQFP塑料方型扁平式封装和PFP塑料扁平组件式封装。三、PGA插针网格阵列封装。四、BGA球栅阵列封装。五、CSP芯片尺寸封装。六、MCM多芯片模块。

其中近年来热门的叠层封装(Package on Package---PoP)，就是有点像盖楼房，搭积木一样，chip里面的die可以叠加在一起，然后chip又可以堆积起来。每次说到这词，我脑海中的第一反应，就是香港那瘦瘦高高窄窄的高楼，密密麻麻；如果做饭炒菜缺盐了，可以伸手出窗户向邻楼借的……

这周在三藩市，同时还有一个太阳能的展会Intersolar. 下次再分享。 Cheers!

Pic: 1. Indium Corporation   2. http://hiphotos.baidu.com/xueyeerr/pic/item/783216d10219aa3e9a502776.jpg

李宁成博士Dr. Ning-Cheng Lee

今天，有幸约到公司的在行业中的全球活招牌---李宁成博士(Dr. Ning-Cheng Lee)---吃个便饭，请教了他对行业动向的一些看法。

1．09年SMT行业的大趋势？

李：（笑"你这个topic很大噢"）主要还是component方面的变化，从2D package 转向 3D package，像盖楼房一样。以前die小，package大；那就在package上下功夫。现在已经是CSP(chip scale package)了，package已经缩小到和die一样了，无法再缩了，那么要继续微型化，就只能3D了，也只有这样可以有更好更快的电子产品。所以PoP (package on package,叠层封装) and 3D die stacking会越来越流行。 

2．基于这个大趋势，SMT行业技术方面的动向，以及其带来的挑战？

李：目前die stacking 主要涉及的是memory die, 因此还没有对散热问题带来挑战。但是以后的micro-processer，除了减小尺寸来增加transistor的个数, 另外一个途径就是stack the die 从而达到微型化的(miniaturization)。  叠了4到5层，micro-processer的个数增加了，功率增加了，散热和可靠性是一个主要的挑战。 

3．最近有许多文章都在讨论SMT工厂兼做太阳能光伏组装（Solar Cell Assembling）的后道工序。您是如何看待的？这会有什么挑战吗？

李：目前应该不会有什么大的挑战。需要解决的技术问题， SMT行业和半导体(Semiconductor)方面，有很多经验/技术是相似的；半导体行业的许多经验，以前都已经转用到SMT行业了。类似的，太阳能光伏组装也可以借鉴这些SMT的经验。这可以协助太阳能行业更好地做到low cost的流程，从而达到grid parity（太阳能电网性价比）。不过至今，似乎还没有SMT厂商在做太阳能光伏组装。我们还是拭目以待吧。

PS: 哈哈，这顿饭除了有一如既往的"听君一席话，胜读十年书"之感，还真的是免费午餐哦。"家事国事天下事，事事关心"；目光炯据，思想深邃的李博士，常常在我叽叽喳喳地说完一些社会现象和个人看法后，能一语中的地指出其本质或是深层次的含义。俗话说"小人谈人，中人谈事，高人谈哲学"；我是小人或中人，谈人又谈事；李博士是高人，能一针见血地指出其中的内涵。看来姜还是老的辣！感谢李博士！

Pic: Indium Corporation

Franoise Queen of 3D甔 von Trapp at last years Device Packaging Conference

I love exciting blogs, they are a change of pace in our industry.  Here's a new one that you should check out: Françoise in 3D.  It offers a growing base of knowledge that is geared towards the evolving field of 3D IC packaging innovation.  I'm not sure where the topic boundaries are set, but I hope we will see some entries regarding package-on-package (PoP) assembly or design.

Good luck Françoise, we look forward to your foresight in this 3 dimensional world!

Have you ever had a hard time getting help with something?  For the last year I’ve been searching for a new vehicle, which can be a long journey for a technically oriented car guy.  The problem has been that the local dealerships in my region are unwilling to take their customers seriously.  The exact car that I was interested in sits only 13 miles from where I live, in a showroom.  The salesman who asked me if I needed anything (notice I didn’t say “helped me”) admitted that he didn’t know anything about the car, and that he didn’t want to – since it was to be shipped to somewhere where it would sell.  He then mentioned that my Jeep Wrangler couldn’t be traded in because it was a gas hog and there isn’t a market for those in central NY.  I left disappointed, did I mention I was asked not to sit in the car or open the hood?

The next stop was a dealership 60 miles away.  This dealership would not allow anyone to test drive the Lancer Evolution X.  This time I was allowed to at least sit in the car, check out the engine, trunk, and other components.  Still, no test drive = no sale.

I was done wasting time with salesmen that had no interest selling their performance car.  These guys just wanted to sell economy cars all day.  Easy, but what fun is that?  A dealership 100 miles away told me over the phone to stop by and try out the car.  A test drive is all I needed, and I left the dealership with a new car that day.

Why does this relate to us?  I don’t expect you to make big decisions about ball attach fluxes, flip chip fluxes, package-on-package pastes, or bumping materials without feeling confident you are getting the right product for your application.  Sure, a car isn’t a consumable item like flux or solder – but I understand that you need to spec in the materials that you use and it can be a pain to change.  Let’s get it right the first time!

~Jim  

For a change of pace, again, I have asked another Technical Support Engineer, Chris Nash, to comment about powder sizes.  Chris is the Regional Technical Support Engineer for the Midwest region, and works from Indium Corporation HQ in Clinton, NY.

What’s the difference between Package-on-Package (PoP) / BGA rework solder paste, and solder paste designed for SMT?  Solder paste for dipping applications is designed to transfer more solder based on its rheological characteristics.  In the chart shown here, a typical SMT paste is compared to 3 next generation dipping pastes.  Although the names cannot be released right now, all PoP/rework pastes transferred over 100% more paste to the solder joint area.  (Hint: you can probably break me down relatively easily if you have me on the phone.  For the whole story call me at (315) 853-4900)

This added solder volume helps ensure that more solder is available during joint formation to compensate for component warpage.  During rework, increased solder volume replaces solder that has been scavenged during the component removal process.  Either way, more solder volume relates to a more robust solder joint.

 

• Are you looking for information on semiconductor packaging materials?  Send your request to jhisert@indium.com.  It’s all fair game – released, experimental, or competitor materials.  Flux characteristics, paste properties, application methods…

   

  Inquire about any of the following topics:

  • Pin transfer
  • Package-on-Package (PoP)
  • Solder spheres
  • Glass transition temperatures (Tg)
  • Flip chip assembly
  • BGA rework
  • Cross-sectioning electronic components
  • Paste for component dipping
  • Solder alloys
  • Liquid fluxes
  • Wafer bumping
  • Low alpha solder
  • Spin coating
  • Redistribution layers (rdl)
  • Halogen-free
  • Flux viscosity
  • Solder paste viscosity
  • Whatever else you are interested in

A new tutorial on assembling package-on-package components is available.  Click here for the PoP Guide and other application notes.

Just because a Design Of Experiment (DOE) doesn’t turn out the way it was conceived, that doesn’t mean it can’t be a beautiful thing.  There is great merit to achieving what you set out to do, and in most cases that should happen.  With mature processes and materials we have a good chance of following through with our goals.  With new processes and materials there is a better chance that you can learn such important information during testing that the test matrix may need to be modified – and that is okay.

The key to adjusting a DOE is being able to make good quick decisions and leveraging the data that has already been collected - when possible.  For instance, if it is the first time you have ever evaluated Package-on-Package assembly materials there may be some things that you had planned that need adjustment.  I certainly wasn’t sure if my target settings would work when our Package-on-Package work began.  Another thing that will help you become flexible with your testing is making sure you have some spare chips/components and substrates, just incase you need to explore another set of variables that were not obvious before. 

It’s not the end of the world if problems occur while you’re testing materials, in fact things can turn out even better if you relax, re-evaluate the situation, and redesign your experiment accordingly.   

 

From a mechanical perspective, larger solder joints are generally preferred when assembling package-on-package (PoP) components.  Just as a large set of gears can handle more power, fortified interconnects add a measure of reliability to BGAs and CSPs.  That is why in many cases, dipping paste is used instead of PoP flux for package-on-package stacking and BGA rework - to increase solder joint volume.  The added volume of solder helps keep the solder spheres in contact with interconnect pads throughout the reflow cycle, combating the effects of warpage.  This will help you increase the solder reliability and the final yield of your PoP assemblies.

Here are some links to learn more about the PoP solder paste process:

Control Your Materials, or They Will Control You (part 1)

Control Your Materials, or They Will Control You (part 2)

Package-on-Package Paste Leveling (1/5)

Package-on-Package Component Dipping (2/5)

Package-on-Package Placement (3/5)

Package-on-Package Transport (4/5)

Package-on-Package Reflow (5/5)