Indium Corporation Blogs

While on a recent trip to Malaysia, I interviewed two colleagues regarding trends in semiconductor assembly. My previously-published interview with Sze-Pei Lim appears here.

This time, while on a visit to a logic device manufacturer in the North West, I [ACM] talked briefly to Sehar Samiappan [SS], Indium Corporation's Area Technical Manager, about our recently-developed water-soluble pin-transfer Ball-Attach Flux, WS446-NRD, which is designed for BGA applications of 0.5mm pitch, and greater than 1500  I/Os.

[ACM] What is the origin of WS446-NRD?

[SS] The development was driven by a customer need for a guaranteed good quality BGA (ball-grid array) solder joint, but with reduced environmental impact. Our very quality-focused customer uses several different suppliers of organic FC-BGA substrates with copper OSP pads. The customer had serious concerns about occasional poor solderability of SAC305 solder spheres onto substrates. The key defect seen was poor wetting onto the OSP-coated copper pad, which would give rise to variability in both joint strength and bump coplanarity,  and even (in worse cases) missing-ball / “big ball” effects. Some of the pad finishes were seen to be highly oxidized, severely restricting solder wetting during reflow. Variability in the surface finish was found to be not just from supplier to supplier, but also showed up as lot-to-lot variability from lower cost suppliers.

Some of the differences seen could be attributed to the method of mask desmear from the C4 “cage” of the flip-chip (top side) area, which was either a plasma-based desmear or an oxidizing inorganic acid dip, that was clearly having effects on solderability of the opposite (bottom) BGA side of the substrate.

[ACM] What steps have customers previously taken to get around this issue?

[SS] This is a serious issue for many ball-attach flux users, and some customers have gone to the lengths of using a special fluxing step to remove contaminants such as oxide and OSP (organic solderability protectant) coatings. These liquid fluxes are very reactive, but require  separate spraying, reflow, and cleaning stages that add cost and time. The halogenated ball-attach fluxes of the WS446 series have an established good chemistry that allows wetting of SAC105, 305, and 405 onto a variety of metallizations. In the semiconductor assembly industry, the WS446 fluxes are well-known in Taiwan, and throughout South East Asia, for their good solderability and long pot-life in a variety of FC-BGA applications.

[ACM] What was different about WS446-NRD, and why was it developed?

[SS] WS446 fluxes are all colored, using a bright red dye, so the flux can be seen by eye and automatically detected by vision systems. Red coloration also allows automated ball-attach flux dipping replenishment systems to detect flux levels. Normally, colored fluxes are not a problem, but the customer had some environmental concerns with the red color contaminating the water-wash equipment, and building up in their water-recycling system. WS446-NRD was developed from the basic WS446 flux series chemistry, but  without the red dye. The solderability performance of WS446-NRD was excellent, eliminating the variations in OSP solderability without requiring any additional processing steps. WS446-NRD also passed internal process and product requirements, such as cleanability, and the customer was very pleased with Indium’s ability to rapidly tailor a chemistry to their specific requirements.

[ACM] Sehar: thank you. I look forward to sharing a durian with you again when they are back in season.

7月份，我有幸去了景色迷人的三藩市(San Francisco)参加Semicon West展会，并听了“The 2.5 & 3 D packaging landscape for 2015 and beyond”的技术讲座。 这是我第一次参加半导体方面的展会，虽然2.5D 和3D packaging等相关词语听多了，但是真正含义是什么，也是直到最近才真正了解。 上周Triquint Semiconductor的齐权博士(Dr. Quan Qi)给我进一步讲解后，才又“豁然开朗”了许多。

简单来说吧，2.5D就是还要依靠一层Interposer来叠加，而不是直接logic & memory叠加到substrate上面。 而3D packaging 就能真正做到logic & memory到substrate上的直接多层叠加。齐博士给我举了一个很好的例子为什么现在很多公司还是在做2.5D，而不是3D,主要是3D有很大的CTE Mismatch. 比如说Logic & Memory的CTE 是3ppm, 但是substrate是17ppm。 在如此微型化的今天，很多小球（sphere）和pad就会因为CTE的大差别而错位。 如果引入了一层interposer, 就能够缓冲CTE mismatch 的问题。

 2.5D 和3D packaging各自的优劣势，存在的问题和挑战，专家们都在这个演讲稿里面有自己详细的分析，如果有兴趣，很值得阅读参考：“The 2.5 & 3 D packaging landscape for 2015 and beyond”

Indium Corporation能够为2.5D 和3D packaging提供各种Flip-Chip, Package-on-Package, 和Ball-Attach 之间的连接材料和解决方案。 欢迎参考: http://www.indium.com/products/semiconductorpackagingassembly.php

Cheers! 

 

Picture Resource: Dr. John Xie’s (Altera Coproration) presentation in Semicon West  2012. 

 

About a month ago I posted about the various 3D technologies (chip creation, packaging and printed circuit boards) that are being used to optimize the various electronics upon which we all rely.  Molded Interconnect Device (MID) technology has been around for more than 20 years and is being used extensively in cell phone antennae. 

Recently I discussed the state of the art of 3D-MID technology with the Director of 3D MID Technology at Cicor in Switzerland, Nouhad Bachnak.  Cicor is one of the key players in the development of molded interconnect devices.

Carol: MID technology has been around for more than 20 years but, so far, it is only widely adopted in cell phone antennae.  What is sparking the renewed interest for other electronic applications?

Nouhad: The idea to use 3D-MID for electronic applications is much older than the idea to use this technology for antenna applications.  When this technology started in the 1980's there was a high euphoria that it would replace the printed circuit board (PCB).  But there was a lack of qualified materials and a lack of specific know-how for the manufacturing process.

Over the last few years a tremendous amount of development work has been done and considerable progress was made.

New MID-specific design, chemical and 3D assembly machines were developed and successfully implemented in serial production.  Millions of antennae have been produced, but also several other products like sensors, switches and LED carriers for automotive, medical and industrial applications show the benefits of 3D-MID and this encouraged customers to use them.

Carol: What processes do you offer for making these devices and what are the benefits of each?

Nouhad: We use the LPKF Laser Direct Structuring (LDS) and the 2S (two shot molding) processes.  These two processes have to be seen as complementary to each other, rather than competing with each other.

Major advantages of the LDS process are:

• Simple injection molding tool
• Easy layout changes (just by changing the CAD layout)
• Thin structures are possible 150 µm or even smaller

Major advantages of the 2S process are:

• Only two process steps for the substrate manufacturing (molding and plating)
• High reproducibility of the layouts
• Very economical for big plating surfaces and complex layouts

Carol: What are the biggest challenges facing component attachment to 3D-MID?

Nouhad: The first one is the 3D attachment of the components on the MID substrate.  Precise 3D electronic assembly systems with several axes and sophisticated optical systems are required to master this task accordingly.  In this area we are working with Haecker Automation, who develops such high-standing quality systems.  The other aspect is the capabilities of the substrates to withstand high temperature solder profiles.  There are of course several materials which can withstand up to 260C.  But these materials usually have some other weaknesses (fragile, too expensive).

Carol: What markets are showing the most interest in using this technology to replace traditional printed circuit boards?

Nouhad: Using the benefits of 3D-MID is not limited to certain markets.  3D-MID can be used everywhere, where plastics meets electronics and it is not just about replacing PCB.  3D-MID opens a tremendous amount of possibilities by using MID as an interconnectivity module combining electrical and mechanical functions in one part.

Carol: What do you see as the key drivers in moving MID forward in the electronics industry?

Nouhad: The key drivers in moving 3D-MID forward are:

• Miniaturization: due to space problems (automotive, medical, telecommunication, etc.)
• Rationalization and system simplification: reduction of process steps, number of parts and mounting time
• Functionality: new functions which are made possible only because of the high functional integration possibilities, design flexibility and the precision given by 3D-MID

The 3D-MID technology advantages in these areas are:

• Optimal three dimensional space utilization
• High function integration density of mechanical and electronic functions
• Saving of parts and process steps

Carol: Where do you see the industry in another ten years?

Nouhad: This is the most difficult question!  In this context I would like to quote the famous physicist Nils Bohr: "Forecasts are always difficult-especially if they concern the future".

Nevertheless one thing seems to be evident: the 3D-MID technology has already gained a footing in the market and is growing very fast.  For our part, for the next three years, Cicor is planning its manufacturing capacities according to growth rate expectation of more than 50% per year.

 

 

Thanks Nouhad for your time and expertise. 

Like we have often said about indium metal, the possibilities are endless®!

Carol Gowans

 

 

 

 

 

Browse the coming attractions at your local movie theater.  How many 3D movies are being advertised?  3D is a very exciting technology for movie and TV watchers, and the future of it may be based in three other 3D technologies.

Let's start with the initial building block of any electronic device, the chip.  Wikipedia describes the 3D Chip as: "a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit."   The result is a chip that is faster, smaller, and consumes less power than a single layer chip.  This is a fairly new technology that has been developed in the last five years and is still gaining popularity.

The next phase of manufacturing, and the area where we focus, is 3D Packaging.  When you stack several chips (regular or 3D) together, you are performing 3D Packaging or Package on Package (PoP) or System in Package (SiP).  This is also a fairly new technology but it is widely used.  As with the 3D chip, the goal of this technology is to provide a faster, smaller device that consumes less power.  Dr. Andy Mackie, Semiconductor Assembly Materials Product Manager here at Indium Corporation, recently blogged about his graphic representation of the complex 3D Packaging processes.  He has included the 3D and the 2.5D packaging into his chart which will be on display at Semicon West 2012.

Once you have the chips, you need a substrate to attach them to -  that is the final 3D technology.  3D MID (molded interconnect device) is a technology that has been around for about 20 years. Typical rigid substrates constrain design and are generally less adaptable to the tiny devices being designed today.  Flexible substrates open up the design possibilities with the ability to twist and turn as needed.  3D MID are made out of lighter materials (like thermoplastics) than rigid substrates and can be molded into a variety of 3D shapes.  This allows for greater design possibilities while producing a substrate that is lighter and more compact.  In automotive applications this can translate to lighter vehicles that need less fuel to operate.  Of course there are the challenges of incorporating the circuitry into the thermoplastic and then soldering to the non-flat (sometimes vertical) surfaces.  This technology will be discussed at the 10th International Congress on 3D MID Technology in Germany in September.

Like most new technologies, the many facets of 3D start off expensive and are not widely adopted.  But as new manufacturing techniques are developed to reduce cost, 3D TVs and all the 3D electronic assembly technology that may support them will become increasingly common place.

Photo from Cicor.

Carol

Indium metal has the unique ability to cold weld (bond) to itself at room temperature. Though this is, technically, not soldering, this property makes it especially useful for low-temperature bonding applications. Back in 2008 I mentioned indium cold welding on the semiconductor packaging blog. Here are some other resources for learning more about the process:

• The official Cold Welding Application Note
• Using indium in a cryogenic seal application.
• Using indium in Flip-chip applications

Cold welding is a great solution to some really tricky bonding applications. Some nice features of using indium cold welding as a bonding method are:

1) It offers an instant attachment. Because indium will stick together upon physical contact (with a slight amount of pressure) the bonding process takes a fraction of a second as opposed to reflow soldering processes for solders or curing processes for epoxies – which can take seconds to many minutes.

2) It requires no heat. Temperature-sensitive components can be assembled without heating. The stresses that occur due to CTE (coefficient of thermal expansion) are also not an issue, which makes this a great process for attaching large dissimilar CTE materials like brittle ceramics and high expansion rate metals.

3) The bond will have exceptional thermal and electrical conductivity due to the nature of the indium that is used for this process.

You can use the indium cold welding process on any material you can successfully sputter, evaporate, reflow, or plate indium onto.

The answer to the age-old question: “What is the expected lifetime and associated strengths of an indium cold weld?” is:

The cold weld bond will last indefinitely and the bond strengths approach that of a solid piece of indium, 273 PSI.

If you have questions, please email them to askus@indium.com.

My friend and colleague Chris Nash and I were recently discussing some puzzling results for low dip height found during testing of package-on-package (PoP) materials. The findings will be of interest to everyone who uses a dipping process in both SMT and flip-chip assembly. Firstly, a little background. Many of you will be familiar with the two types of dipping tray used in both PoP and flip-chip assembly:


Advantages have been claimed for both types of system, but the rotary type seems to be winning out over the linear type for very precise dip depth control. That said, linear seems to be much more common. Why should this be?

One clue that we recently discovered is that the dip depth for a linear system is always less than the designed depth: whether the fluid in it be a flux or a dipping solder paste. The assumption is that the depth of flux in the linear dip tray is exactly the same as the design height (below).


However, as evidenced by both visual inspection of the solder ball / flip-chip bump dip height, and also by direct measurement of the fluid in the dip tray, the actual flux or paste dip height is always less than the design height (below). Why should this be?

The answer can probably be found in reference to the concept of a boundary layer (red circle above): a layer of material immediately adjacent to a surface that is either completely immobile (static boundary layer) or moving at a velocity less than in the bulk of the moving fluid. With no boundary layer, there would be no drag (fluid frictional forces) and of, course, that is why golf balls have dimples: so that the boundary layer is kept mostly beneath the outer surface of the ball, to reduce drag. This principle has also been adopted for some squeegee blades.

The reduction in height is of the order of 10-20microns, as closely as we can tell with the measurement systems available. So, for a 200micron dip depth, this will only lead to an error of -5 or -10% in the actual dip height.

Since most dipping materials are thixotropic, there is the added complication of time dependence of the material's rheology. The fastest way to reach the equilibrium dip depth is to use a very fast movement of the doctor blade system relative to the dipping tray, although this will almost inevitably increase the prevalence of bubbles.

Again, the linear system is most commonly seen for most PoP and flip-chip dipping applications, but it clearly has its limitations, as we will discuss in part II.

I welcome your comments.
Cheers!  Andy

One of the first activities any child enjoys, once they can manipulate things, is using paints and crayons to color pictures. Stay with me: there's a reason for this introduction.

In the last six months, we have had many requests from customers concerning a flip-chip or ball-attach flux with which they are very happy, and which is qualified for their process. The customer simply asks: "By the way, can you make it colored?" The reasoning here seems to be that if a three year old can color a picture, then it should be easy for an Indium Corporation flux chemist to simply just, surely..?

The answer is that what seems simple is, in reality, very complicated, and I will touch on just some of the reasons why.

Engineers seem very surprised when you ask them, in response, why they need the color. Often, the reply comes back, "So I can see it." It is here that one of the problems starts: once you are dealing with a question of human perception (that is, the fallibility of human eyesight, plus the problems inherent in the brain processing the image), there is a large variety of variables which you then have to pin down:

 1/ What color?

 2/ How wide and thick is the deposit?

 3/ What shape is the deposit?

 4/ Which do you want to determine?: the location of the flux / how much flux is present / the shape of the flux deposit / presence or absence of flux / something else?

 5/ What standard will you use to determine 4/?

 6/ What lighting will you be using?

 7/ What optical system (microscope / cameras) will you use?

 8/ How will you benchmark the ability of different operators to see the flux?

As we have found in many instances, a flux color-level that will allow an automated replenishment system to operate may give flip-chip flux deposits that may be almost invisible to the human eye.

I haven't finished! Once this has been determined (and we will not be able to perfectly replicate the customer inspection process), then you have all the effects of adding the coloring chemical to the flux. As any of our formulation chemists will tell you: there is no such thing as a "small" change in a flux. Further questions arise:

 9/ Pre-reflow flux or post-reflow residue?

    - Post-reflow may not be feasible

 10/ Usage affects chemistry available and choice of color:

    - Color agent concentration needs to be optimized so other properties of flux are not affected
    - Experience shows thin films of colored flux are undetectable by eye or vision systems

 11/ Addition of even small quantities of the coloring agent will affect the physical properties to some extent:

    - Rheology: Tack / viscosity / pot-life (usage life)
    - Reflow / wetting / voiding
    - Coloring agent may also affect the electrical properties (SIR/ECM) of a no-clean flux!

12/ Water-insoluble color agent can stain substrates and cause cross-contamination within the reflow oven or final cleaning system.

    - NOTE: The most effective (deeply colored) color agents are not very water soluble.

13/ Color agent must be homogeneously distributed, especially for sub-100micron pitch flip-chip and copper pillar applications.

    - Manufacturing process and QA testing methods need to be developed for each flux and color chemistry

Finally: Yes, we do have several colored fluxes: some red; some blue; some black, and some fluorescent. Does this mean that they will automatically work in your inspection process? Not by a long piece of sidewalk chalk. I hope you now understand why.

Still interested? Contact me.

Cheers!  Andy

This post was prompted by a Korean customer, who this month asked what the limitations are for aqueous (water-based) cleaning for fluxes used in copper-pillar flip-chip applications. How low can the pitch get before aqueous cleaning becomes unfeasible / impractical?: 40microns? 20microns? 5microns?

Good question. I don’t have a definitive answer, but I do now have an industry consensus that seems to be consistent. I’ll try to answer the query in a little while, but firstly, you’ve got to ask, "What is 'aqueous' cleaning?" Is it:

-        Deionized (DI) water?

-        Water plus a surfactant?

-        Water with a saponifier?

-        Mixed phase (oil /aqueous phase)?

-        All of the above?

DI water alone may be an ideal cleaning fluid from both a reliability and a “green” perspective, but its poor wetting onto even mildly hydrophobic surfaces, high viscosity compared to many low molecular weight organic solvents, and poor solvency for many molecules used in fluxes (resins are a good example) make it a poor choice as a pure solvent. 

It is also important to distinguish between saponifiers and surfactants:

- Surfactants: Usually a nonionic surfactant: most commonly a hydrophilic polyethylene glycol moiety with a hydrophobic carbon chain attached
-  Saponifiers: Usually basic chemistry that chemically reacts with high molecular weight acids in RMA and no-clean fluxes

Adding surface-active agents (surfactants) to water will help it to wet to less hydrophilic surfaces, and so help it move into confined spaces. The advantage of a nonionic surfactant over an ionic one is two-fold; a) there are no potentially ionic residues to cause electrical problems if improperly rinsed off b) the optimum surface-wetting enhancement (so-called “CMC”) is at a much lower surfactant concentration, but note that this also makes it more difficult to rinse off completely.

The general structure of the most common nonionic surfactant is:

               CxHy-(OC₂H₄)_n-OH

On the other hand, the way the saponifier works is a simple acid/base reaction, usually using amine chemistry:

               R’R”NR’” + RCO₂H ---> R’R”NR’”H+ + RCO₂-

The purpose of the basic saponifier is to massively increase the solubility of resins in aqueous solutions, while the surfactant is simply a means of enhancing wetting onto hydrophobic surfaces. Where it gets complicated, is when you realize that the saponified resin is now also capable of acting as a surfactant.

The reason I bring this up is that for smaller pitch flip-chip applications, we are now predominantly seeing the use of small amounts of nonionic surfactants with deionized water, along with other tricks to get the aqueous solution under the chip.

I think I’ll stop there. More next time. Meanwhile, feel free to comment or to email me on this.

Cheers! Andy

最近小忙，少讀書了，也少和大家分享了；不過工作之餘，翻看了一下《A Seat at The Table》一書，覺得裏面有些道理也蠻有啓發的。比如説此書中一直圍繞這個主題來展開了論述“Today, the only thing your customer cares about is value.”

就這個觀點，再對照一下Indium公司的兩個主要系列產品：

²       電路板組裝焊接材料(Solder Materials):  這裡也要分產品而論。對於技術含量較高，工藝使用要求較多的焊錫膏(Solder Paste)材料，重視成品可靠性的客戶們會更多的關注產品帶來的“價值”。 如果只圖便宜的材料，但是用起來“錯漏百出”的，最後還是事倍功半：返工，復修，廢棄率高（特別是浪費貴的不能翻修的板子），產出率低，總體成本也自然高了。 對技術含量較低，工藝已經“模式化”的產品，像錫棒(Solder Bar)，錫綫(Solder Wire),  性价比會更關鍵……在目前日益高漲的金屬原材料市場中，Indium公司考慮到客戶們的成本壓力，也推出了性能可以和SAC305錫棒媲美的有成本優勢的Sn995錫棒。

 

²       半導體封裝材料(Semiconductor Materials):  整個半導體行業應該算是一個高成本，高投資，高回報（運營得好的話）的三高行業。半導體封裝材料也像是其中的經絡血脈吧，連接各個部分，讓整體最後順暢無阻的工作。半導體各個部分的材料都不便宜，設備更是不菲；對材料性能的表現要求和驗證都很嚴格，畢竟都投資那麽多，不能“功虧一簣”嘛。所以客戶們一般會十分重視產品的價值。 Indium 公司目前提供的半導體材料有：Wafer Flux, Wafer Paste, Micro Spheres, Flip-Chip Flux, Substrate Paste, Ball Attach Flux, Die-Attach Paste/Wire, PoP Fluxes, etc. 

 

Indium公司還為大家提供散熱界面材料(Thermal Interface Materials)，工程焊料(Engineering Solders)，薄膜光付太陽能板製造材料&太陽能板組裝焊接材料(PV Solar Materials)，和銦金屬及其化合物等。 這些材料使用在比較領先的應用中，新興行業，或是細分市場中，客戶們都十分重視產品和服務能給自己帶來的價值。

Cheers!  

Pic: Indium Corporation

PS: 前些日子看了中央4台的《第三屆漢語橋在華留學生漢語比賽》，感慨不已！除了感嘆這些留學生們對“那麽難”的漢語的精湛掌握，對中國文化和歷史的了解，甚至對中國的熱愛；更感慨的是，這些活動也説明了祖國的強大！現在越來越多的留學生們來中國學習，想進一步了解中國，和中國人民交流；中國話也在慢慢傳播到全世界！以前中國學子們苦讀英語，考TOFEL, 雅思，GRE什麽的；現在金髮碧眼的學生們也在場上比拼誰更了解我們的“四書五經”了，哈哈！

 

Those of you have been watching this blog for a while will know that I’ve been keeping tabs on the status of the European ELV (End-of-life vehicle) legislation on lead (Pb), mercury (Hg), cadmium (Cd) and hexavalent chromium (Cr^VI). It’s been both galling and heartening at the same time, to find that when I Google “elv legislation”, this (my) blog keeps coming up as one of the top 10 sources on the subject. OK: enough of the bloggy, solipsistic prevarication...

 

My friend, Geert Willems of IMEC late last week let me know that the EC (European Commission) had given its final decisions on Annex II ("the exceptions"), and pretty much adopted the recommendations of the Öko Institute from their 127 page report of September last year (2009). I have to say my hat is off to Dr. Otmar Deubzer of IZM and Stéphanie Zangl of Öko for the very thorough and logical background to this legislation.

 

The decisions that affect those of us in the semiconductor (flip-chip) and power semiconductor arena are primarily the ones on lead (Pb) in solders, that were formerly covered by section 8.a/ and 8.b/ of the old, outdated Annex II to Directive 2000/53/EC, and are now covered by this new legislation.

 

A quick visual summary of the legislation relevant to lead (Pb) in electrical interconnects is given below, and please consult the original document for confirmation, as I may have missed some subtlety of the legalese in my quest for brevity. Also, frankly, subsection 8 (b) led to some Transatlantic confusion over whether finishes on pin connectors and PWB's were covered(?), but I think the below is correct:




Refer to the table below for the timeline for of each subsection/exception:



Note that the last review of exemptions was carried out in 2009, with potential effect by 1/1/2011. This implies that the legislative hammer will potentially fall on each of those usages slated for future review on January 1st two years after the review year. Lead (Pb) for most electronics attach usages of interest to those of us in semiconductor and power semiconductor packaging may therefore be "legislated out" by 1/1/2016.

Basically, the use of Pb-containing solders in solder paste, die-attach paste, die-attach wire, solder preforms, and thermal interface materials (TIMs) in automotive electronics assembly is safe for now, and changes will not be forced on the automotive electronics assembly industry at a time when even current manufacturing practises may be leading to still-unresolved safety incidents.

Cheers!  Andy

The use of gold layers deposited onto nickel is standard in many industries, from DRAM memory module edge connectors, to electrical test probe contacts, to power semiconductor die metallizations and wirebonding pads. While the role of gold in the final solder joint is well-understood, I wanted to learn more about the gold deposition process from an industry expert, so was given the chance to discuss this with Lenora Toscano, MS, Final Finish Product Manager with MacDermid.

 

Andy Mackie: What role does gold play in protecting surfaces in SMT and semiconductor assembly processes?

Lenora Toscano: Gold does not form an oxide; it protects the nickel from oxidation or passivation. A clean nickel surface has very high solderability for most solder types, but its oxide is very difficult to remove with standard flux types. Also, gold dissolves almost instantaneously into most solders during assembly, thus promoting superior wettability.

 

Andy Mackie: What standards exist on the thickness of gold for different electronics and semiconductor assembly applications?

Lenora Toscano: The main application of ENIG (electroless nickel/immersion gold) coating is in chip-on-board (COB) technology, the typical thickness of the immersion gold layer on the HDI substrate being 3-5 micro-inches.

 

Edge connectors typically require the use of hard gold. Acid gold deposits are used for compliance with MIL-STD-275, which states that gold shall be in accordance with MIL-G-45204, Type II, Class 1. The thickness shall be 50-100 micro-inches, typical thickness is 30-50 micro-inches on 150micro-inches nickel.

 

On the other hand, for solderable surfaces, typical thickness is 5-15 micro-inches on 150micro-inches nickel.

 

For wire bonding, in general, gold plating of a minimum of 30 micro-inches on 200 micro-inches nickel works well. Soft gold is generally preferred. Soft gold processes are also used for boards designed for semiconductor chip (die) attachment. These qualities comply with Type I and III of MIL-G-45204.

  

Andy Mackie:  What are the differences between gold layers deposited by immersion gold and electroplated gold processes?

Lenora Toscano: There are five main differences:

1. The coating thickness is different. Immersion gold is a displacement reaction, gold displaces the nickel on the surface, and is self-limiting as the nickel surface is coated with the immersion gold. Common baths cannot produce thicknesses of much more than 10 micro-inches, while with electroplated gold the thickness depends on current and time. The higher current or longer the plating time the thicker the gold coating.
2. The structure of the gold deposit layers is different. Electroplated gold is denser that the naturally porous immersion deposit.
3. The hardness is usually different. Electroplated gold often has other metals introduced into the plating that make the deposit harder.
4. Porosity is different. Immersion deposits have more porosity that electroplated deposits; it is the nature of the plating system.
5. Deposition composition (purity) varies with additives in the bath. Immersion gold baths contain gold as the only plated metal, while electroplating systems may introduce small amounts of other metals.

Andy Mackie: How thick does gold have to be to fully protect the underlying surface, and what are the trade-offs as customers attempt to reduce their gold costs?

Lenora Toscano: Per IPC-4552 ENIG specification, 1.97 micro-inches is the recommended minimum at +/-4 sigma from the mean, with 3 – 5 micro-inches being typical.

 

The immersion gold deposit is porous by definition. It does offer very good protection to the underlying nickel, but over time the porosity of the deposit results in the passivation of the nickel surface and the wetting forces will be reduced. Of course, this process should take years to occur, but if the gold coating is too thin (below the minimum requirement), it will occur sooner and affect the solderability. 

 

Andy Mackie: What advantage does gold have over silver or other metals?

 

Lenora Toscano: Again, gold has good tarnish resistance and solderability after storage because it does not form an oxide or hydroxides, so it is unaffected by temperature and storage conditions that might reduce the shelf-life of the other finishes. It meets requirements for lead-free (Pb-free) assembly while offering a coplanar surface that is both solderable and aluminum-wire and gold-wire bondable.

 

Gold has good electrical conductivity, and produces a contact surface with low electrical resistance. Electroplated gold is also an excellent etch resist.

 

Electroplated silver is not widely used in the printed circuit industry. Under certain conditions or electrical potential and humidity, silver will migrate along the surface of the deposit and through the body of insulation to produce low-resistance leakage paths. Alkaline cyanide baths for silver electroplating are highly toxic.

 

Immersion silver is susceptible to problems if not correctly stored and even packaged. Packaging materials that contain sulfur or allow exposure to air will result in tarnishing of the surface (sulfide, sulfate, and chloride formation). High levels of surface contamination can detrimentally affect solderability.

---------

Lenora - many thanks for your time, and  for sharing your expertise with us.

Cheers! Andy

After you've reflowed solder in contact with a flux, you're always left with a certain amount of flux residue. There are no clear industry guidelines on how you refer to the residue, and new terminology is emerging all the time. If you leave it up to me, here is what I recommend : 

1/ "No clean" flux residues:

- Standard Residue:  >40%
- Low Residue (LR): Between > 10% to 40%
- Ultralow Residue (ULR): Between >2% to 10%
- Near Zero Residue (NZR): Between 0 to 2%

Each % is given as the weight percent of flux residue after a real reflow process, and refers to the fraction of the raw flux, or flux component of a mixture (such as solder paste or metal-filled epoxy). Note that the exact amount of residue will vary with the reflow profile; the mass of flux or solder paste studied; and the rate of gas flow over the sample material, as well as secondary factors, such as the oxygen level in the reflow atmosphere.

Thermogravimetric analysis (TGA) is a pretty poor method for determining post-reflow residue levels. Results from the use of a platinum TGA sample cup with nitrogen flowing over it have been found in our testing to vary significantly with the mass of sample present, probably because the headspace in the cup acts as a "dead zone" for entrapment of vapor: TGA may therefore give artificially high % residue readings, compared to the results on a flat leadframe or other substrate.

From the viewpoint of a standard semcionductor assembl process, now consider the situation of a low-clearance direct chip attach "flip-chip" or package-on-package application, where the flux is essentially entrapped in a "cage" of I/O's, sandwiched between two flat diffusion barriers. As well as issues of flux residue, this also raises the question of how the electrical properties of the flux will be affected, if more of the solvent and other volatiles from the flux are trapped in the residue.

2/ "Water-soluble" (same principles apply for "Solvent cleanable") flux residues:

- Water-soluble: Residues can be truly dissolved in water to leave a transparent liquid: the color of the this rinse liquid is immaterial,
- Water-dispersible: Non-transparent rinse liquid with any hint of translucency or turbidity

I know that the differences here will be very dependent on rinse-water quality and temperature; chemistry of any cleaning agents; stage of bath-life and so on, but to my mind, if the rinsed liquid is not transparent, then the solids from the flux must be suspended as fine particulates. These particulates usually have refractive indices different from the bulk liquid: the result - turbidity. There may be a means of bath-life end-point determination by turbidity or dynamic light scattering (DLS) or a similar technique; possibly in combination with the standard refractive index measurement that is most commonly used.

In conclusion, note that ULR and NZR fluxes are showing increased usage in flip-chip applications, since these types of material interfere less with the curing of underfill polymers. NZR fluxes are becoming critical for copper-pillar bumping applications.

Just my thoughts - let me know what you think.

Cheers!   Andy

去年看奥运，都是在电视中"景仰"壮观的鸟巢和水立方，特别是那色彩斑斓的夜景。上个月在北京，最开心的事情之一，就是终于一睹鸟巢的风采了。

或许是有点职业病吧，现在只要在晚上一看见五颜六色的大型建筑物的外层装饰，就想起这很有可能是LED的应用，而且以后的发展趋势，很有可能使用更高亮度(High Bright: HB) 和高功率(High Power: HP)的LED. 

高亮度LED，在未来的应用领域中，除了可以给大型建筑物提供装饰照明，还可以用于户外照明，全球各种轿车中的前灯照明，LED投影仪/电视，甚至寻常百姓家的照明等。这里有些文章，是关于LED照明产业的市场规模和预测。

为了解决LED的技术瓶颈之一，散热问题，Indium公司为大家提供一系列焊接和散热材料，如LED制造中的第一层贴装die attach, 或是后几道工序中的substrate attach, 排列成矩阵，甚至是固定LED矩阵列的base plate attach。欢迎随时与我们交流！ask@indium.com , china@indium.com  

 

PS: 真的是有点职业病了：上个月在深圳，友人带我经过深圳的CBD(Central Business District)时，我说"DBC晚上的夜景不错嘛。""小姐，这是CBD吧？…"哈哈，那段时间和许多团队交流新产品信息和技术，我满脑子都是DBC---这是IGBT模组中的核心电路芯片(Direct Bonding Chip)。Indium公司为IGBT模组的生产和制造商，提供各种焊接材料和散热材料！ Anyway, CHEERS！ 

It’s no secret that I love WS3622.  The water soluble flux is a magic bullet for all types of semiconductor packaging applications.  As a tech guy, you need to be able to trust a flux – I trust this one.  It can be used for flip-chip attachment, sphere mounting, wafer-level bumping, and a variety of odd jobs. 

 

Since I began describing the flux to coworkers and customers, I have always mentioned that it is red and it has the appearance of ketchup.  Without going into my [over]use of ketchup, I guess that description stuck because it’s another material that is near and dear to my heart. 

 

Today I noticed that WS3622 really bares more of a resemblance to red acrylic paint.  I think it’s the smooth texture of the flux that really makes its consistency more like acrylic paint than ketchup.

One of these chameleons was my former pet, the other was a fake model.  Interestingly, they are the same if you only ask certain questions about them.

·          Is it green?

·          Is it a lizard?

·          Does it have four legs?

The difference becomes apparent when you start asking the right questions

• Does it change color?
• What does it eat?
• Is it alive?

You must also ask the proper questions regarding halogen-free ball attach fluxes and flip-chip fluxes.

• How is it tested?
• What is the ppm level of Br, Cl, F?
• Does the material pass per j-std-709?

 

Make sure your getting the “Real Green”.

I am well aware that many of you are now working in stressed out, short-handed workplaces and your workloads have increased significantly. With hundreds of solder alloys, forms, and flux chemistries to choose from, it is a difficult (and potentially time-consuming) decision to determine which will best suit a product design. I understand why product engineers miscalculate the effects of chip component choices, or let solder materials be assumed based on historical convention, but hasty decisions open the door to product failures in the field. My expert solder team and I are here to help you make the best solder design decision as efficiently as possible so that this doesn't happen to you.

When stretched thin, design mistakes happen to the best of us. For example, according to Andy Patrizio, Apple has encountered the misfortune of field failures with one of their most reputable products – the MacBook Pro. Solder serves a number of purposes (in this case as an electrical and mechanical connection) and on the most basic level, the solder must serve these as well as maintain joint integrity for a given amount of time. This can almost always be achieved with a little thought and engineering. According to Patrizio however, the 9600M discrete NVidia graphics chip in the MacBook Pro was designed with chip-attach materials that are failing. The operational temperature of the chip is melting the solder completely. 

In the least arrogant way possible, I'd like to make it clear that this chip attach issue would have been simple to prevent had the expertise of my engineering team been enlisted. Let us be your "call-a-friend" lifeline.

Au stud bumped flip chip attachment?  Low temperature assembly requirements? Indium is your answer…

 

Indium can be used in many ingenious ways to attach flip chips.  It can be used for solder interconnections, cold-weld attachments, and even low temperature solid-state diffusion bonding.  The pliable nature of indium allows it to perform well during reliability testing - such as temperature cycling.

 

Have you ever had a hard time getting help with something?  For the last year I’ve been searching for a new vehicle, which can be a long journey for a technically oriented car guy.  The problem has been that the local dealerships in my region are unwilling to take their customers seriously.  The exact car that I was interested in sits only 13 miles from where I live, in a showroom.  The salesman who asked me if I needed anything (notice I didn’t say “helped me”) admitted that he didn’t know anything about the car, and that he didn’t want to – since it was to be shipped to somewhere where it would sell.  He then mentioned that my Jeep Wrangler couldn’t be traded in because it was a gas hog and there isn’t a market for those in central NY.  I left disappointed, did I mention I was asked not to sit in the car or open the hood?

 

The next stop was a dealership 60 miles away.  This dealership would not allow anyone to test drive the Lancer Evolution X.  This time I was allowed to at least sit in the car, check out the engine, trunk, and other components.  Still, no test drive = no sale.

 

I was done wasting time with salesmen that had no interest selling their performance car.  These guys just wanted to sell economy cars all day.  Easy, but what fun is that?  A dealership 100 miles away told me over the phone to stop by and try out the car.  A test drive is all I needed, and I left the dealership with a new car that day.

 

Why does this relate to us?  I don’t expect you to make big decisions about ball attach fluxes, flip chip fluxes, package-on-package pastes, or bumping materials without feeling confident you are getting the right product for your application.  Sure, a car isn’t a consumable item like flux or solder – but I understand that you need to spec in the materials that you use and it can be a pain to change.  Let’s get it right the first time!

 

~Jim  

 

Die assembly often involves a number of process steps, and may include a solder thermal interface. High temperature solders such as AuSn or SAC solders have been used by some, but a subsegment of the market have overlooked these completely because their chips and assembly components cannot withstand the high temperature soldering that these alloys require. Another solder material that has been considered is indium. Indium has a higher conductivity than these other alloys, is much more compliant, and melts at a significantly lower temperature. Indium solder die attach is a preferred material by many. For an even smaller market subsegment, this method of indium solder attachment still poses issues. It may be that the melting temperature even of pure indium (156C) is too hot or that they cannot use the flux that is required with a soldering process. These customers are looking for a material with the performance of a solder TIM, but room temperature curing temperatures and a flux-free application. Polymer TIMs are what these manufacturers often settle for, but there are other higher performing options to be aware of. One option is a room temperature application of indium. This process involves the pre-attachment of indium to both the backside of the die and substrate. The pre-attachment can be done either with pre-reflowed preforms, or plated indium. Both indium surfaces are cleaned and indium will cold weld to itself. A solder joint has been formed with all its benefits, and the device has not been exposed to any elevated temperatures. For more information on the indium cold welding process, read: Jim Hisert's Blog entry on Indium Bonding and Indium Cold Welding or the Indium Cold Welding Application Note.

 

Michael Qiu supports Indium Corporation in Eastern China.  I thought an interview with him would be a good chance to see the semiconductor industry from a different perspective.

邱学丞服务于铟泰中国华东区。采访他会是个从另一个角度去认识半导体行业的绝好机会。

 

Jim: How long have you been involved in the semiconductor industry in China?

吉姆：你在中国从事半导体行业多久了？

Michael: I have been in the semiconductor industry in China more than three years. Before that, I spent four years learning IC design, IC manufacture and Package in a University in Shanghai.

邱学丞：有三年多了。在这之前我花了四年时间在上海某大学学习IC设计、制造 (Fab)和封装。

 

Jim: What semiconductor materials are most popular for your customers?

吉姆：在你的客户中哪些半导体材料用的比较多？

Michael: For some semiconductor package customer, silver epoxy is very popular applied to do die attach. As for high power device, paste/SSDA is used popular for die attach. But for some advanced customers who do BGA, FC and WLCSP business, flux or fine power paste is required.

邱学丞：在一些封装厂里，银浆被大量地用来贴芯片于框架上。对那些做大功率器件的客户来说，锡膏或者焊线用来贴芯片比较普遍。而那些做BGA, FC和WLCSP的客户，他们需要的则是助焊剂或者精细颗粒锡膏。

 

Jim: What trends do you see in semiconductor package manufacturing in China?

吉姆：你觉得中国半导体封装的趋势如何？

Michael: For [cost sensitive] customers who do Diodes/Transistor package, the manufacture cost will be more and more important.

BGA/FC/CSP package share will increase soon in the near future and more factories will be able to do those packages.

More advanced package like SIP (system in a package) and MCM (multi-chip module) will [become] popular, but this may take several years.

邱学丞：对那些制造二极管或三极管的客户来说，成本对竞争力非常重要。他们对材料的成本以后会愈加敏感。在封装市场中，BGA/FC/CSP市场份额会有迅速的增长，而且会有更多的厂家能做这些封装。还有一些更高端的封装技术，比如SIP (system in a package) 和MCM (multi-chip module) 会开始流行，当然这得花个好几年时间。

 

Jim: What topics would our customers in China like to see in the Semiconductor Packaging Blog?

吉姆：中国的客户希望在半导体封装博克上看到什么样的话题？

Michael: Our customers always hope to get our professional technical support. They prefer the blog on a particular application or issue. For example, comparison between In and AuSn in LD die attach and use dilute hydrochloric acid to remove oxidation layer on In preforms.

邱学丞：我们的客户总是会希望能得到更好的专业支持。他们会比较喜欢主题明确，针某个具体应用或者问题的一些文章。比如：“LD芯片贴装应用中In和AuSn的对比”和“用弱盐酸去除铟焊片表面的氧化物”。

 

Jim: What is the most exciting thing about the semiconductor industry to you?

吉姆：半导体行业中什么东西最让你觉得激动？

Michael: A chip which is smaller than your nail has so many functions.

邱学丞：一个比你指甲还小的芯片能拥有如此多的功能，这太迷人了。